hdl: Work on the registers. Renaming in progress.

- mode is now 4 bits
- no default mode with jumpers
- all fp inputs sync'ed with gc_sync_ffs
- data from interface controller sampled on rising edge of sys_clk


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78745 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Continue clean-up.

- simpler pps counter
- gc_extend_pulse for LED monostable
- generic up/down counter module
- clean sci decoder (was P2Serial)
- add cvrob decoder (from Damien Perrelet BE/RF)
- more renaming on top level


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78746 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Work in progress. Re-writting serial decoders.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78747 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Work on rtm serial data manager.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78748 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Work on ram manager.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78749 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Clean-up, version with new 2x16 and cvorb modes. To be tested.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78750 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Rename package, use numeric_std instead of std_logic_unsigned and std_logic_arith.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78751 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Rename files, rename ports and signals on top entity, use extend_pulse from general-cores for dac load pulse generation.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78752 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Add script to generate .xsvf file from .bit


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78753 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Remove unused files.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78754 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Rename .bit file in xsvf geenration script.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78755 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Add makefile for xsvf generation, add ise project and reports.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78756 0a99fbf0-06a5-4c52-8a11-fe70044ee989
doc: Add notes on gateware test procedure.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78757 0a99fbf0-06a5-4c52-8a11-fe70044ee989
doc: Starts moving user manual to texinfo.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78758 0a99fbf0-06a5-4c52-8a11-fe70044ee989
all: Re-organise folder structure.

Add synthesis makefile and release script.
Remove xilinx/ folder (not used any more).
Rename cpld project and sources folder.
Move fpga related stuff to the hdl/ folder.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78759 0a99fbf0-06a5-4c52-8a11-fe70044ee989
all: Rename src/ folder in rtl/.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78760 0a99fbf0-06a5-4c52-8a11-fe70044ee989
struct: Rename rtl/ folder in src/


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78761 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Update manifest and ise project with new folder structure.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78762 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Use STROBE only for parallel data input and sample/store data on CLOCK in all modes.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78763 0a99fbf0-06a5-4c52-8a11-fe70044ee989
hdl: Sync data inputs to sys clock (parallel and cvorb modes).
     Positive input polarity by default, polarity now selectable by csr reg.
     Module disabled by default.
     Module must be disabled to change mode (protected in gateware).
     When no sampling clock, frequency meter shows 0.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cvora@78764 0a99fbf0-06a5-4c52-8a11-fe70044ee989