ARM: tegra: power: Re-factor core voltage capping

Re-factored core voltage capping APIs:

- Collapsed set level and enable APIs into one set level interface;
non-zero level automatically enables capping, and zero level disables
capping. Attempt to apply new non-zero level before the previous one
is disabled is rejected.
- Added error reporting and propagation through api layers
- Allowed to set cap voltage at nominal vdd core level even if voltage
to frequency mapping is not ready (no clock rates are capped at nominal
voltage, anyway).

Core voltage capping APIs are not used by any kernel client (designated
to vdd core override mechanism, yet to be added). Hence, function names
and signatures changes are transparent, for now. User space vdd core
capping sysfs nodes are not affected and kept backward compatible.

Bug 1246712

Signed-off-by: Alex Frid <afrid@nvidia.com>

Change-Id: I66343c77e1bae337b8c829d98fb98dc75fc9a971
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/221526
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Tao Xie <txie@nvidia.com>
Tested-by: Tao Xie <txie@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Matt Wagner <mwagner@nvidia.com>

Conflicts:
	arch/arm/mach-tegra/dvfs.h