DebugInfo: Avoid creating unnecessary/empty line tables and remove the special case of '0' in DwarfCompileUnit::initStmtList by just always using a label difference

This moves one case of raw text checking down into the MCStreamer
interfaces in the form of a virtual function, even if we ultimately end
up consolidating on the one-or-many line tables issue one day, this is
nicer in the interim. This just generally streamlines a bunch of use
cases into a common code path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205287 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Do not convert to cmp32 for Atom arch by Sergey Okunev

Differential Revision: http://llvm-reviews.chandlerc.com/D2824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205288 91177308-0d34-0410-b5e6-96231b3b80d8
Recover TableGen/LangRef, make it official

Making the new TableGen documentation official and marking the old file as
"Moved". Also, reverting the original LangRef as the normative formal
description of the language, while keeping the "new" LangRef as LangIntro
for the less inlcined to reading language grammars.

We should remove TableGenFundamentals.rst one day, but for now, just a
warning that it moved will have to do, while we make sure there are no more
links to it from elsewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205289 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Rewrite MipsAsmParser and MipsOperand.

Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: fix bug in ld3r (1d) SelectionDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205293 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: add patterns for more lane-wise ld1/st1 operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205294 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Hoist Parser.Lex() calls out of MatchAnyRegisterNameWithoutDollar()

Summary:
No functional change

Depends on D3222

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3232

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205295 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Use AsmLexer::peekTok() to resolve the conflict between $reg and $sym

Summary:
Parsing registers no longer consume the $ token before it's confirmed whether it really has a register or not, therefore it's no longer impossible to match symbols if registers were tried first.

Depends on D3232

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3233

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205297 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Extend ParseJumpTarget to support the full symbol expression syntax.

Summary:
This should fix the issues the D3222 caused in lld. Testcase is based on
the one that failed in the buildbot.

Depends on D3233

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3234

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205298 91177308-0d34-0410-b5e6-96231b3b80d8
Fixing warnings in the MSVC build. No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205301 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205302 91177308-0d34-0410-b5e6-96231b3b80d8
Fixing an MSVC warning about widening the result of a 32-bit shift implicitly. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205304 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Renamed ParseAnyRegisterWithoutDollar to MatchAnyRegisterWithoutDollar

This is for consistency with other functions. The Parse* functions consume
tokens and the Match* functions don't.

No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205305 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: add cyclone CPU with ZeroCycleZeroing feature.

The Cyclone CPU is similar to swift for most LLVM purposes, but does have two
preferred instructions for zeroing a VFP register. This teaches LLVM about
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205309 91177308-0d34-0410-b5e6-96231b3b80d8
Attempting to fix r205124, which had failed asserts when built with MSVC.

Suggestion from Yaron Keren.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205313 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: teach LLVM that Cortex-A7 is very similar to A8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205314 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ThumbLE/ThumbBE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205317 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify debug_loc.dwo handling slightly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205322 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup remaining use of removed variable to fix the build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205323 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: Factor out common functionality for rendering debug_loc and debug_loc.dwo location list entries

In preparation for refactoring this function into two, one for
debug_loc, one for debug_loc.dwo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205324 91177308-0d34-0410-b5e6-96231b3b80d8