fix write line to colour ram.
change colour ram to default to yellow, instead of blinking, reverse, bolded grey.
make all VIC-III extended character attributes conditional on the
ATTR register.
reenable CIAs now, since CS issues should be fixed
make simulatable in ghdl
create simulatable versions of xilinx block rams for simulation.
workaround for colourram location $0000 getting overwritten glitch.
try to fix problem with CIAs not tristating properly when CS=0.
add missing cia6526 module.