ARM: 7493/1: use generic unaligned.h

This moves ARM over to the asm-generic/unaligned.h header. This has the
benefit of better code generated especially for ARMv7 on gcc 4.7+
compilers.

As Arnd Bergmann, points out: The asm-generic version uses the "struct"
version for native-endian unaligned access and the "byteshift" version
for the opposite endianess. The current ARM version however uses the
"byteshift" implementation for both.

Thanks to Nicolas Pitre for the excellent analysis:

Test case:

int foo (int *x) { return get_unaligned(x); }
long long bar (long long *x) { return get_unaligned(x); }

With the current ARM version:

foo:
	ldrb	r3, [r0, #2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
	ldrb	r1, [r0, #1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
	mov	r3, r3, asl #16	@ tmp154, MEM[(const u8 *)x_1(D) + 2B],
	ldrb	r0, [r0, #3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
	orr	r3, r3, r1, asl #8	@, tmp155, tmp154, MEM[(const u8 *)x_1(D) + 1B],
	orr	r3, r3, r2	@ tmp157, tmp155, MEM[(const u8 *)x_1(D)]
	orr	r0, r3, r0, asl #24	@,, tmp157, MEM[(const u8 *)x_1(D) + 3B],
	bx	lr	@

bar:
	stmfd	sp!, {r4, r5, r6, r7}	@,
	mov	r2, #0	@ tmp184,
	ldrb	r5, [r0, #6]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 6B], MEM[(const u8 *)x_1(D) + 6B]
	ldrb	r4, [r0, #5]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 5B], MEM[(const u8 *)x_1(D) + 5B]
	ldrb	ip, [r0, #2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
	ldrb	r1, [r0, #4]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 4B], MEM[(const u8 *)x_1(D) + 4B]
	mov	r5, r5, asl #16	@ tmp175, MEM[(const u8 *)x_1(D) + 6B],
	ldrb	r7, [r0, #1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
	orr	r5, r5, r4, asl #8	@, tmp176, tmp175, MEM[(const u8 *)x_1(D) + 5B],
	ldrb	r6, [r0, #7]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 7B], MEM[(const u8 *)x_1(D) + 7B]
	orr	r5, r5, r1	@ tmp178, tmp176, MEM[(const u8 *)x_1(D) + 4B]
	ldrb	r4, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
	mov	ip, ip, asl #16	@ tmp188, MEM[(const u8 *)x_1(D) + 2B],
	ldrb	r1, [r0, #3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
	orr	ip, ip, r7, asl #8	@, tmp189, tmp188, MEM[(const u8 *)x_1(D) + 1B],
	orr	r3, r5, r6, asl #24	@,, tmp178, MEM[(const u8 *)x_1(D) + 7B],
	orr	ip, ip, r4	@ tmp191, tmp189, MEM[(const u8 *)x_1(D)]
	orr	ip, ip, r1, asl #24	@, tmp194, tmp191, MEM[(const u8 *)x_1(D) + 3B],
	mov	r1, r3	@,
	orr	r0, r2, ip	@ tmp171, tmp184, tmp194
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

In both cases the code is slightly suboptimal.  One may wonder why
wasting r2 with the constant 0 in the second case for example.  And all
the mov's could be folded in subsequent orr's, etc.

Now with the asm-generic version:

foo:
	ldr	r0, [r0, #0]	@ unaligned	@,* x
	bx	lr	@

bar:
	mov	r3, r0	@ x, x
	ldr	r0, [r0, #0]	@ unaligned	@,* x
	ldr	r1, [r3, #4]	@ unaligned	@,
	bx	lr	@

This is way better of course, but only because this was compiled for
ARMv7. In this case the compiler knows that the hardware can do
unaligned word access.  This isn't that obvious for foo(), but if we
remove the get_unaligned() from bar as follows:

long long bar (long long *x) {return *x; }

then the resulting code is:

bar:
	ldmia	r0, {r0, r1}	@ x,,
	bx	lr	@

So this proves that the presumed aligned vs unaligned cases does have
influence on the instructions the compiler may use and that the above
unaligned code results are not just an accident.

Still... this isn't fully conclusive without at least looking at the
resulting assembly fron a pre ARMv6 compilation.  Let's see with an
ARMv5 target:

foo:
	ldrb	r3, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
	ldrb	r1, [r0, #1]	@ zero_extendqisi2	@ tmp140,
	ldrb	r2, [r0, #2]	@ zero_extendqisi2	@ tmp143,
	ldrb	r0, [r0, #3]	@ zero_extendqisi2	@ tmp146,
	orr	r3, r3, r1, asl #8	@, tmp142, tmp139, tmp140,
	orr	r3, r3, r2, asl #16	@, tmp145, tmp142, tmp143,
	orr	r0, r3, r0, asl #24	@,, tmp145, tmp146,
	bx	lr	@

bar:
	stmfd	sp!, {r4, r5, r6, r7}	@,
	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
	ldrb	r7, [r0, #1]	@ zero_extendqisi2	@ tmp140,
	ldrb	r3, [r0, #4]	@ zero_extendqisi2	@ tmp149,
	ldrb	r6, [r0, #5]	@ zero_extendqisi2	@ tmp150,
	ldrb	r5, [r0, #2]	@ zero_extendqisi2	@ tmp143,
	ldrb	r4, [r0, #6]	@ zero_extendqisi2	@ tmp153,
	ldrb	r1, [r0, #7]	@ zero_extendqisi2	@ tmp156,
	ldrb	ip, [r0, #3]	@ zero_extendqisi2	@ tmp146,
	orr	r2, r2, r7, asl #8	@, tmp142, tmp139, tmp140,
	orr	r3, r3, r6, asl #8	@, tmp152, tmp149, tmp150,
	orr	r2, r2, r5, asl #16	@, tmp145, tmp142, tmp143,
	orr	r3, r3, r4, asl #16	@, tmp155, tmp152, tmp153,
	orr	r0, r2, ip, asl #24	@,, tmp145, tmp146,
	orr	r1, r3, r1, asl #24	@,, tmp155, tmp156,
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

Compared to the initial results, this is really nicely optimized and I
couldn't do much better if I were to hand code it myself.

Change-Id: If51a8ef5e3276d922629b21e724063dc31591f49
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7583/1: decompressor: Enable unaligned memory access for v6 and above

Modern GCC can generate code which makes use of the CPU's native
unaligned memory access capabilities.  This is useful for the C
decompressor implementations used for unpacking compressed kernels.

This patch disables alignment faults and enables the v6 unaligned
access model on CPUs which support these features (i.e., v6 and
later), allowing full unaligned access support for C code in the
decompressor.

The decompressor C code must not be built to assume that unaligned
access works if support for v5 or older platforms is included in
the kernel.

For correct code generation, C decompressor code must always use
the get_unaligned and put_unaligned accessors when dealing with
unaligned pointers, regardless of this patch.

Change-Id: I3041cac765854d25f2b585b5626ec09098b3e539
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
lib/lzo: Rename lzo1x_decompress.c to lzo1x_decompress_safe.c

Rename the source file to match the function name and thereby
also make room for a possible future even slightly faster
"non-safe" decompressor version.

Change-Id: Ife1f8a30741b1c35c2596fe72d891f7532eee0d1
Signed-off-by: Markus F.X.J. Oberhumer <markus@oberhumer.com>
lib/lzo: Update LZO compression to current upstream version

This commit updates the kernel LZO code to the current upsteam version
which features a significant speed improvement - benchmarking the Calgary
and Silesia test corpora typically shows a doubled performance in
both compression and decompression on modern i386/x86_64/powerpc machines.

Change-Id: Ieea74335f29c749e0304048d8190058db0b309ad
Signed-off-by: Markus F.X.J. Oberhumer <markus@oberhumer.com>
lib/lzo: huge LZO decompression speedup on ARM by using unaligned access

Change-Id: I19599cd91aa394af51ab3cb1a66aa9cfd36c4962
Signed-off-by: Markus F.X.J. Oberhumer <markus@oberhumer.com>
lzo: properly check for overruns

commit 206a81c18401c0cde6e579164f752c4b147324ce upstream.

The lzo decompressor can, if given some really crazy data, possibly
overrun some variable types.  Modify the checking logic to properly
detect overruns before they happen.

Change-Id: Ide9f7b9a97e5c04521d30416f7a83c0f23b98851
Reported-by: "Don A. Bailey" <donb@securitymouse.com>
Tested-by: "Don A. Bailey" <donb@securitymouse.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ks01lte: Enable optimized AES and SHA1 routines

Change-Id: If8b580160bb06f746e0c05f867115396790b10c1
cyttsp4: Fix mrproper.

Change-Id: Iff0b8a5b13dfaa22e6e6ee399fba04cdb9f8b288
ext4: limit the number of error prints

Use printk_ratelimit instead so as to avoid large number of prints
from the EXT4 in case of error.

Change-Id: Id160cda919429d9045f804876bc736ff87419860
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
fat: limit the number of error prints

Use fat_fs_error_ratelimit instead of fat_fs_error so as to
avoid large number of prints.

CRs-Fixed: 619824
Change-Id: I458df6c2c7a53c0902f2b388b5992007b719cb86
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
block: Fixes after dm-crypt merge.

Change-Id: I0e0e7f04c31e330a90559d5187b6872a38090b19
mmc: block: check for NULL pointer before dereferencing

mmc block data can be NULL. Hence, check for NULL before
dereferencing md.

Change-Id: Ie5188014750d0f8ef9faac97689933f81b3160c4
CRs-Fixed: 562259
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
fs: proc: Remove unneeded code.

Change-Id: I2171af2b974bb05f8608c0d9d6d84d43228335e3
ks01lte: Disable exfat. Use ext4 for ext2 and ext3.

Change-Id: Id76f9b3b73ea09a8064ad007bfe9530d8a731814
fs: ext4: Remove bak file.

Change-Id: I60ab4b0c0cadb31d996d39b6303259e2456b90b0
dwc: Sync with Samsung source.

Change-Id: Ic95f631b31bbd732f43bef3199676ac3c5839a28
USB: dwc3: otg: Fix stop endpoint command timeout issue

Currently HSPHY SUSP bit is set while starting host mode and
it is not cleared till stopping host mode. As part of urb dequeue,
xhci stack will queue stop endpoint command for flushing endpoint
which is getting timedout due to this HSPHY SUSP bit. Hence clear
this bit before queuing stop endpoint command and set it back after
stop endpoint command completion. Otherwise xhci stack treats this
timeout as fatal error and halts host controller.

Crs-Fixed: 580268
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>

Conflicts:
	drivers/usb/dwc3/dwc3_otg.c

Change-Id: I5e44390238215da0025f1dfa4602e271fc16e4a3
USB: dwc3: msm: Fix bug during STM enable/disable for QDSS

commit "I0fdc5d703b3fd445e83226534f07743461c96f4c:usb: dwc3-msm:
remove use of global context variable (DBM)" is required for adding
support multiple instances in dwc3-msm driver. This added an incorrect
condition check in the driver before reinitiating USB reconnection
for STM enable/disable. Due to this, QDSS doesn't work when STM tracing
is disabled and enabled. Hence Fix this issue by using proper check.

CRs-Fixed: 523344
Change-Id: I6302396c7bf03cd2313e5d571e0aef51648a2258
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
usb: dwc3: Enable newer refclk-based SOF/ITP generation

Add support for refclk-based SOF and ITP generation, which is
present on DWC3 cores starting in revision 2.50a. This supersedes
the functionality provided by GCTL.SOFTITPSYNC which handled ITP
generation only. This introduces the new GFLADJ register and
writes its fields based on the reference clock period to the
core, which can now be specified as a device tree parameter.

Signed-off-by: Jack Pham <jackp@codeaurora.org>

Conflicts:
	Documentation/devicetree/bindings/usb/msm-ssusb.txt

Change-Id: I4ca4bcabc4fe782ba711d4f288d75f4e0a852a65
USB: dwc3-msm: Add support for 24MHz utmi clock

For ref clk based SOF/ITP generation, utmi clock needs to be set
to frequencies like 19.2MHz, 24MHz etc. Hence add support for
setting utmi clock to 24MHz.

Change-Id: Ia64eaa5320846ab219c516f43e6dcdf0fb05eb89
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>