position_calc_core/*: wishbonization in progress
Merge branch 'devel' into pos_calc_wishbonized

Conflicts:
	hdl/modules/wb_position_calc/wb_position_calc_core.vhd
hdl/modules/wb_position_calc/*: top module iface change

Removed redundant valid signals for all position data
rates. The actual DSP chain still uses them, but they will
be removed soon.
hdl/*/wb_position_calc/wbgen/*: update wbgen files

 - Included registers for reading Monit. Amplitudes and
Monit. Position data.

 - Fix some fields with wrong "clock" description.

 - Fix some fiels with wrong "access_*" description
 	for MONOSTABLE type regsiters

 - Fix size of K* registers. Changed from 26 to 25 bits wide.

 - Regenerated files from wbgen2.
hdl/sim/regs/wb_pos_calc_regs.vh: update verilog constants
hdl/*/wb_position_calc/*_counters*: add error counter

Added error counters for various DSP signals
hdl/*/wb_position_calc/*_pkg.vhd: update DSP package

Added error counters modules to package
hdl/*/wb_position_calc/*: update top position_calc modules

 - Removed top interface error and configuration signals. They
 	are now accesible only through the Wishbone interface.

 - Added error counter modules

 - Output Monit. amplitude and Monit. position data to
 	Wishbone registers. They can be read through
	polling the registers, as change slowly and
	are used only to check tendencies and slowly
	changing variations.
hdl/modules/wb_position_calc/Manifest.py: update Manifest

Now, it includes the error counters modules
hdl/modules/dsp_cores_pkg.vhd: update top files interface

 - Updated top "position_calc" files interface

 - Moved SDB records to this file. They were located
	 on the bpm-sw repository. It makes more sense
	 to reference them here.
hdl/modules/*: change location of SDB structures again.
hdl/modules/wb_un_cross/*: update wbgen files

 - Change gain register to 16-bit

 - Change naming of wbgen files
hdl/*/wb_position_calc/wbgen/*: update wbgen files

 - Update position calculation Wishbone signals
 	to use fs_clk2x clock
hdl/modules/*/wb_position_calc_core.vhd: use fs_clk synchronized signals

Change Monit. Amp and Monit. Pos signals to use fs_clk
synchronized signals instead of fs_clk2x ones
hdl/modules/wb_position_calc/*: removed bogus files

Removed merge-generated files. They were not supposed
to be committed ever.
hdl/modules/position_calc/generated/*: add script to build manifests

This script creates a Manifest.py file from a set of .vhd,
.v and .ngc files
hdl/modules/wb_position_calc/wb_*: change CDC fifo size to 16
hdl/modules/*/wb_position_calc_core.vhd: don't use sys_clr for now

This was causin a shift in the TDM streams as not all blocks
implement sys_clr synchronization properly. See issue #15 in
https://github.com/lerwys/dsp-cores/issues
models/ddc_bpm_476_066.mdl: Simplified Monit. PFIR Filter

The previous Monit. PFIR had a long group delay
(40 -- 10 Hz -- clock cycles) which caused a 4s delay
to output. Now, it has a group delay of 1.5 clock cycles,
which accounts for less than 0.2s.
hdl/modules/position_calc/generated/virtex6/*: update generated files

The previous Monit. PFIR had a long group delay
(40 -- 10 Hz -- clock cycles) which caused a 4s delay
to output. Now, it has a group delay of 1.5 clock cycles,
which accounts for less than 0.2s.