mach-tegra: Low Power core overdrive

This overdrive unlocks the low power core (LP)'s full potential of 620 MHz

Signed-off-by: Paul Reioux <reioux@gmail.com>

Conflicts:
	arch/arm/mach-tegra/cpuquiet.c
sound/soc/tegra/tegra_pcm: add min CPU perf lock for audio playback

this should resolve the audio underruns which resulted in audio clicks and
pops while transitioning from idle to busy.

Signed-off-by: Paul Reioux <reioux@gmail.com>

Conflicts:

	sound/soc/tegra/tegra_pcm.c
arm: tegra: Set Core to 0.95V in LP1

When the device prepares for LP1, the Core voltage is set to the
highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and
Cardhu). This is to set for some of the driver suspend along the
sequence need a higher emc frequency and thus a higher Core voltage.

Since the sequence of drivers suspend depends on the sequence of
their registration in the table, which in turn is platform-dependent,
there is no right place in the LP1 entry path where the Core voltage
can be set to a lower voltage. Hence, the Core voltage remains high
in LP1 resulting in higher power.

Thus, the only safe location where the Core voltage can be lowered is
once all the drivers are suspended and the DRAM is set in self-refresh,
at the final point just before the system is suspended in the IRAM code.
This location at the assembly code ensures that no other module will be
running and thus that nothing will require a higher core voltage. The Core
is set to the lowest possible value since nothing requires it. It is then
restored to the highest voltage as soon as the LP1 resume code is started
so that all drivers are resumed safely.

At the execution point in IRAM during LP1 suspend path, even the I2C clocks
are gated. They must be reset first and then the I2C transaction is performed.
An I2C transaction involves 4 bytes of data, to send the slave address,
the Core voltage register address and 2 bytes of data which has the value
to set the voltage(the second byte is not required for this transaction).
Once these registers are set, the I2C transaction is performed by setting
the I2C transaction register to 0xA02. After sending the I2C transaction,
we wait for about 250us to check the status of the transaction and if not
updated, wait for more time to check again. If after 2ms and the transaction
fails to register, the transaction is aborted and the device is allowed
to enter at high voltage. Since the failure rate of I2C transaction is very
low at this point in execution where there will be no conflicts in the bus,
it is okay to have Core high for some of the LP1 cycles.

However, it is unacceptable for the I2C transaction to fail on the way
from LP1 resume since the device cannot come up with a lower Core
voltage. In this case, the transaction is retried again and again till
it is successful. There is no way but to keep trying as the device
would fail to resume with Core at 0.95V.

Each platform(or each PMU) has different values for the I2C transaction
ie. slave address, Core voltage register and the value to set the
voltage. For the device in IRAM, it cannot access anything in SDRAM
memory, these values needs to be pushed to IRAM memory before the device
starts execution in IRAM. This is done during initialization of suspend
code when it picks values from the board files and copies it to IRAM
part of code, before the whole memory is copied to IRAM.

This new feature is controlled by a KConfig variable TEGRA_LP1_950 which
should be enabled once the board file of the device is updated with the
right values. The device hangs when it does not have the right values for
the I2C transaction.

With this change in Core, LP1 power is reduced by 12mW in Enterprise,
20mW in AP37 and about 24mW in Kai.

Bug 1035684

Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
(cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296)
Reviewed-on: http://git-master/r/124779
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
adapted to use for Nexus Grouper from NV reference

Signed-off-by: faux123 <reioux@gmail.com>
arm: tegra: Board files settings for LP1 0.95V CoreV

Set the register values for each of the board files to
keep the Core voltage to 0.95V in LP1.

This change is only for those platforms where LP1 is supported.
Enterprise and Kai are the main platforms for this change. There
is no support for Cardhu for LP1 and so is left blank and the
feature will be skipped for Cardhu platforms, except for AP37.
AP37 with a PM269 board needs this change and so Cardhu board
file is updated with the values specific to AP37.

This change is part of the feature to set VCore to 0.95V
Refer to http://git-master/r/124135 for more details
Bug 1035684

Change-Id: I6d1d984b0e7968b441cebbc37705c25647a4a85a
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
(cherry picked from commit b46921e475bd95e729896a6763bc94df1e03ee4a)
Reviewed-on: http://git-master/r/124780
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
adapted for use on Grouper from NV reference

Signed-off-by: faux123 <reioux@gmail.com>
cpufreq: interactive: Add Uevent Signal on Gov Start

Sends kobject_uevent signal back to userspace to signal that
the cpufreq governor has been set to interactive

Bug 1039141

Change-Id: I699e9d5834a1874b36c675764c080112ccba0f9f
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/131224
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
adapted for Grouper from NV reference

Signed-off-by: faux123 <reioux@gmail.com>
cpufreq: interactive: Unify Governor Lock Strategy

Change our locking strategy to be the same as the conservative
and ondemand governor for GOV_START and GOV_STOP to allow
for correct handling of multiple CPUs

Bug 1049258

Change-Id: I15ab620e2f9d47b00ec8186c224eb719b9735aa7
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/133360
Reviewed-by: Satya Popuri <spopuri@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
adapter for Grouper from NV Reference

Signed-off-by: faux123 <reioux@gmail.com>
Add support for kexec-hardboot

"Allows hard booting (i.e., with a full hardware reboot) to a kernel
previously loaded in memory by kexec.  This works around the problem of
soft-booted kernel hangs due to improper device shutdown and/or
reinitialization."
More info in /arch/arm/Kconfig.

Original author: Mike Kasick <mike@kasick.org>
These patches are ported from Asus TF201, to which it
was ported by Jens Andersen <jens.andersen@gmail.com>.

Change-Id: Ibee734f61ffa97577bfbcdd9a8cd567bd2d89f32
bq27541: Add current_now property

Fix what I broke when I merged with 3G kernel updates from Google :p

Signed-off-by: faux123 <reioux@gmail.com>
bq27541: Add current_now property

Fix what I broke when I merged with 3G kernel updates from Google :p

Signed-off-by: faux123 <reioux@gmail.com>
scripts: remove localversion "+" from kernel version strings

Signed-off-by: faux123 <reioux@gmail.com>
Revert "cpufreq: interactive: Unify Governor Lock Strategy"

This reverts commit 191877acbcf564ce8601b5324d505cebce9b974f.
overall_stats: add overall stats for all available cores

this is much more accurate stats tracking than just displaying core 0's
stats from most other kernels

Signed-off-by: Paul Reioux <reioux@gmail.com>
overall_stats: make dual/quad core stats configurable via meunconfig

Signed-off-by: faux123 <reioux@gmail.com>
CPU hotplug, writeback: Don't call writeback_set_ratelimit() too often during hotplug

The CPU hotplug callback related to writeback calls writeback_set_ratelimit()
during every state change in the hotplug sequence. This is unnecessary
since num_online_cpus() changes only once during the entire hotplug operation.

So invoke the function only once per hotplug, thereby avoiding the
unnecessary repetition of those costly calculations.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Revert "block: Adding ROW scheduling algorithm"

This reverts commit bda0710213ef21783c6c953081d854e3daff49f4.
block: Adding ROW scheduling algorithm

This patch adds the implementation of a new scheduling algorithm - ROW.
The policy of this algorithm is to prioritize READ requests over WRITE
as much as possible without starving the WRITE requests.

Change-Id: I4ed52ea21d43b0e7c0769b2599779a3d3869c519
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>

Signed-off-by: Paul Reioux <reioux@gmail.com>
block: ROW: Correct minimum values of ROW tunable parameters

The ROW scheduling algorithm exposes several tunable parameters.
This patch updates the minimum allowed values for those parameters.

Change-Id: I5ec19d54b694e2e83ad5376bd99cc91f084967f5
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
block: ROW: Fix forced dispatch

This patch fixes forced dispatch in the ROW scheduling algorithm.
When the dispatch function is called with the forced flag on, we
can't delay the dispatch of the requests that are in scheduler queues.
Thus, when dispatch is called with forced turned on, we need to cancel
idling, or not to idle at all.

Change-Id: I3aa0da33ad7b59c0731c696f1392b48525b52ddc
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
block/row-iosched.c: add support for Linux 3.0.x

Signed-off-by: Paul Reioux <reioux@gmail.com>
block: Add support for reinsert a dispatched req

Add support for reinserting a dispatched request back to the
scheduler's internal data structures.
This capability is used by the device driver when it chooses to
interrupt the current request transmission and execute another (more
urgent) pending request. For example: interrupting long write in order
to handle pending read. The device driver re-inserts the
remaining write request back to the scheduler, to be rescheduled
for transmission later on.

Add API for verifying whether the current scheduler
supports reinserting requests mechanism. If reinsert mechanism isn't
supported by the scheduler, this code path will never be activated.

Change-Id: I5c982a66b651ebf544aae60063ac8a340d79e67f
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>