arm: Add Arm Erratum 773769 for Large data RAM latency.

The erratum-773769 occurs on Arm Coretex-A15 (rev r2p0),
when L2 Data Ram latency is set to 4 cycles or more; or
when ACP is in use, or with L2 Data RAM slice configured.
Therefore, the effective latency as calculated in Table 7-2 of
Cotex-A15 (rev r2p0) trm should be 3 cycles or less.

On Exynos5250 based systems the effective data ram latency
is 4 cycles, since we have DATA_RAM_SETUP bit enabled (L2CTRL[5]=1b'1)
and DATA_RAM_LATENCY bits set to 0x2 (L2CTLR[2:0]=3b'010) therefore,
the effective L2 data RAM latency becomes 4 cycles.
So erratum '773769' occurs causing a corrupted L2 Cache.

This patch gives a workaround to the mentioned erratum, using below
mentioned algo:
----------------------------------------------------------------
if data RAM setup = 1
  then check if effective latency i.e (latency + setup + 1) > 3
  if 'true'
    then clear data RAM setup
      goto branch 'a'
if data RAM setup = 0
  a: then check if data RAM latency > 0x10
    if true then force data RAM latency = 0x10
----------------------------------------------------------------
so that the effective data RAM latency reduces to 3 cycles or less
and hence prevent hitting the erratum.

NOTE: The Exynos5250 based products have already been shipped, which
      makes it impossible to add the change in bootloader, so we are
      adding the required change in kernel.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Olof Johansson <olofj@chromium.org>
Cc: David Garbett <david.garbett@arm.com>
Signed-off-by: Humberto Silva Naves <hsnaves@gmail.com>
CHROMIUM: ARM: EXYNOS: Add machine code to support watchdog reset

This patch clears the reset bits for PMU registers
EXYNOS5_AUTO_WDTRESET_DISABLE & EXYNOS5_MASK_WDTRESET_REQUEST
to support watchdog reset for exynos5.

Change-Id: I52ac9cb6a05117e77676e5ae095490a5ed3ff68b
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Humberto Silva Naves <hsnaves@gmail.com>
drm/exynos: add clock_prepare/unprepare in mixer driver

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Humberto Silva Naves <hsnaves@gmail.com>
drm: hdmiphy: Add necessary i2c_device_id table

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>

Conflicts:
	drivers/gpu/drm/exynos/exynos_hdmiphy.c
CHROMIUM: ARM: MM: Add the workaround of Errata 774769

This patch adds the workaround of Errata 774769 that configure write streaming
on versions of A15 affected by this erratum such that no streaming-write ever
allocates into the L2 cache.

BUG=chrome-os-partner:14297
TEST=build ok, booted kernel

Change-Id: I6b7577c073b5df5482d83a90e28fc4f4c3e08ddf
Signed-off-by: Boojin Kim <boojin.kim@samsung.com>
Signed-off-by: Abhinav Kochhar <abhinav@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/33606
Reviewed-by: Olof Johansson <olofj@chromium.org>

Conflicts:
	arch/arm/Kconfig
	arch/arm/mach-exynos/Kconfig
	arch/arm/mm/proc-v7.S
CHROMIUM: ARM: MM: Add the workaround of Errata 766421

This patch adds the workaround of errata 766421 that adds 'dmb' when changing
the translation regime after conditions that the errata 766421 may occur.
Concretely, Add 'dmb' when changing ASID and secure state for cortex-A15 r0p4.

BUG=chrome-os-partner:14297
TEST=build ok, booted kernel

Change-Id: Ib41b855798b71ecf973578305e81cefe754bb1f4
Signed-off-by: Boojin Kim <boojin.kim@samsung.com>
Signed-off-by: Abhinav <abhinav@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/34991
Reviewed-by: Arjun.K.V <arjun.kv@samsung.com>
Reviewed-by: Olof Johansson <olofj@chromium.org>
Commit-Ready: Doug Anderson <dianders@chromium.org>

Conflicts:
	arch/arm/Kconfig
	arch/arm/mach-exynos/Kconfig