Bring simple CPU header up to date with current CPU doc

change RSR instruction to UNUSED_19.  Use JR instead
FP aliases R5
Add shift types
Bring up to date with current CPU doc - run memcheck.asm successfully

32M, not 16M

Add --harvard
    Run with --harvard to fetch instructions from separate memory,
      like FPGA system does at the moment

Change "size" field to "modifier" since different instructions use it
  differently

Bring up to date with CPU doc
    Implement SHIFT as specified: type field and it's a Format18
    Remove RSR
    Make PUSH implementation look like doc
    Make SYS implementation look like doc
    Implement SWAPCC

Print registers at end if INFO verbosity
    Use "--verbose 2" on command line to get this output
Bring up to date with CPU implementation header.

SHIFT is actually format18.
Delete RSR.
Set r1 to 1337C0DE (leet code) if mem check is successful