MIPS HIGHMEM fixes for cache aliasing and non-DMA I/O.

This patch fixes MIPS HIGHMEM for cache aliasing and non-DMA device
I/O. It does the following:

1.  Uses only colored page addresses while allocating by kmap*(),
    page address in HIGHMEM zone matches a kernel address by color.
    It allows easy re-allocation before flushing cache.
    It does it for kmap() and kmap_atomic().

2.  Fixes instruction cache flush by right color address via
    kmap_coherent() in case of I-cache aliasing.

3.  Flushes D-cache before page is provided for process as I-page.
    It is required for swapped-in pages in case of non-DMA I/O.

4.  Some optimization is done... more comes.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>

Conflicts:
	arch/mips/Kconfig
	arch/mips/mm/c-r4k.c
MIPS: Revert fixrange_init() limiting to the FIXMAP region.

This patch refactors commit 464fd83e841a16f4ea1325b33eb08170ef5cd1f4
(MIPS: Limit fixrange_init() to the FIXMAP region) and correctly
calculates the right length while taking into account page table
alignment by PMD.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
MIPS: rearrange PTE bits into fixed positions for MIPS32 R2.

Previously, code did a runtime check of RIXI and made runtime
shifts/etc to fit into PTE as much as possible PFN.
However, because there is no HUGE page support for MIPS32 R2
there is a way to fit all bits in fixed positions:
PTE low bits are: CCC D V G RI(=R) XI M A W P
TLB refill will do a ROTR 6 (in case of cpu_has_rixi),
or SRL 6 to strip low bits.
All 20 bits PFN are preserved in high bits (4GB in 4KB pages)

For hypotetical HUGE page support on MIPS32 R2 an another
pattern is set (S and H are HUGE page support bits):
PTE low bits are: CCC D V G S H M A W R P
No RIXI is enforced
TLB refill will do a SRL 7,
only 19 bits PFN are preserved in high bits (2GB in 4KB pages)

I assume the 256MB HUGE page + RIXI case may be safely discarded.

Patch also rearrange PTE bits for MIPS64 R2 in fixed positions:
PTE low bits are: CCC D V G RI XI [S H] M A W R P
TLB refill will do a ROTR 7/9 (in case of cpu_has_rixi),
or SRL/DSRL 7/9 to strip low bits in absense of RIXI.
PFN size in high bits is 49 or 51 bit --> 512TB or 4*512TB for 4KB pages

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
MIPS: removal of X bit in page tables for HEAP/BSS.

Patch removes eXecute bit in page tables for HEAP/BSS.
It boosts performance because page marked X is _flushed_
each time after COW/swap from cache even for cache coherent systems
in Harvard architecture (!cpu_has_ic_fills_f_dc).
But even Java JIT uses now a special memory region and sets
execute protection for code explicitly.

Patch also sets eXecute Inhibit protection of HEAP/BSS
on CPUs which supports RIXI like proAptiv.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
MIPS: Add set/clear CP0 macros for PageGrain register

Build set and clear macros for the PageGrain register.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
MIPS: mm: c-r4k: Ensure CCA is set to non-coherent on UP kernels.

In case the YAMON bootloader is being used, it will set the Config0/K0
value to 0x5 if a multicore processor is detected. This may have
undesired effects if a CM is present since certain cache operations
may broadcast and go through the CM even if we run a UP kernel.
Therefore it's best to ensure that we are in non coherent mode
in UP kernels even if CM is present.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS: Add CP0 macros for extended EntryLo registers

Add read/write macros to access the upper bits of the
extended EntryLo0 and EntryLo1 registers used by XPA.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
MIPS: Fix address type used for early memory detection.

In 'early_parse_mem' the data type used for the start
and size of a memory region specified on the command line
is incorrect. If 64-bit addressing is used, the value
gets truncated.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
MIPS: Cosmetic cleanups of page table headers.

   * Clean up white spaces and tabs.
   * Remove _PAGE_R4KBUG which is no longer used.
   * Get rid of hardcoded values and calculate shifts and
     masks where possible.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>