msm_fb: display: Program TILE video frame size in dma ISR

Since, video tile frame size register is single buffered, its
value takes effect as soon as it is programmed. Single buffered
registers like this should be configured very close to the vsync
to prevent issues like flicker or artifacts.
Program this register in dma ISR to prevent flickers and IOMMU
page faults.

Change-Id: Ifa770e4b4f29d6e4070e51388043422cc60e5872
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
msm: msm_fb: Map RGB layers to the max possible size.

IOMMU Page Faults are observed on RGB layers during stability
because MDP is trying to fetch out of mapped area of the buffer.
This patch avoids the issue by overmapping the RGB layers to the
max possible RGB buffer size.

Change-Id: Idc7ac9acad70e351acac5dba2ae43b8731e84d35
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
msm: msm_fb: Fix Regressions because of overmap changes.

Previous MDP overmap change is causing issues with HDMI because of
assumptions about overmap. This patch fixes all such issues.

Change-Id: Ifd2f8a0596d9df08538464bdcdd5946cf84db4d9
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>