sunxi: Fix impedance spelling error

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
k1001l1c should use proper dram file too.

This was broken in:

f0a91836e85: Unify eoma68_a20 and a20_olinuxino_m dram settings

Signed-off-by: Korneliusz Osmenda <korneliuszo@gmail.com>
Reviewed-by: Luc Verhaegen <libv@skynet.be>
sunxi: Add a CONFIG_CLK_FULL_SPEED define

And use it to set the clockspeed when we've successfully configured the pmic.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
axp209: Various fixes from upstream review

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
axp152: Various fixes from upstream review

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: use random parts of SID to set ethaddr

Similar to the USB NIC found on OMAP5uEVM, PandaBoard and BeagleBoard-XM
boards, the sunxi SoCs have a NIC onboard without an embedded MAC address.

Just like the omap used on these boards, the sunxi SoCs do have a unique chip
id, in the form of the 128 bit SID register:
http://linux-sunxi.org/SID_Register_Guide

So mimick the BeagleBoard-XM board code (commit 548a64d8) and use the chip id
to generate a unique fixed MAC address.

We check for the SID not being all 0, since some early A20 batches
shipped without having there SID programmed.

Note we use specific parts of the 128 bits, since some parts indicate the
SoC family / revision, and thus are fixed. The algorithm for this was taken
from the linux-sunxi.org kernels.

Signed-off-by: Jonathan Liu <net147@gmail.com>
[hdegoede@redhat.com: Expanded the commit message with some more info]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: Add qt840a board

This board is indentical to the i12-tvbox board, but it has only 1 dram
ic soldered on, so it uses a 16 bit rather then a 32 bit bus for the dram.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: HYP/non-sec: move switch to non-sec to the last boot phase

Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.

Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: non-sec: reset CNTVOFF to zero

Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: add missing HYP mode constant

In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.

Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add separate section for secure code

In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.

Nothing is using it just yet.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: allow relocation to secure RAM

The current non-sec switching code suffers from one major issue:
it cannot run in secure RAM, as a large part of u-boot still needs
to be run while we're switched to non-secure.

This patch reworks the whole HYP/non-secure strategy by:
- making sure the secure code is the *last* thing u-boot executes
  before entering the payload
- performing an exception return from secure mode directly into
  the payload
- allowing the code to be dynamically relocated to secure RAM
  before switching to non-secure.

This involves quite a bit of horrible code, specially as u-boot
relocation is quite primitive.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add generic ARMv7 PSCI code

Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add the option for a second-stage monitor

Allow the switch to a second stage secure monitor just before
switching to non-secure.

This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: convert arch_fixup_memory_node to a generic FDT fixup function

Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.

[maz: collapsed 3 patches into one, rewrote commit message]

Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec/PSCI: emit DT nodes

Generate the PSCI node in the device tree.

Also add a reserve section for the "secure" code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
sunxi: HYP/non-sec: add sun7i PSCI backend

So far, only supporting the CPU_ON method.
Other functions can be added later.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
sunxi: HYP/non-sec: configure CNTFRQ on all CPUs

CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>