tcp: fix FIONREAD/SIOCINQ

tcp_ioctl() tries to take into account if tcp socket received a FIN
to report correct number bytes in receive queue.

But its flaky because if the application ate the last skb,
we return 1 instead of 0.

Correct way to detect that FIN was received is to test SOCK_DONE.

Reported-by: Elliot Hughes <enh@google.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Neal Cardwell <ncardwell@google.com>
Cc: Tom Herbert <therbert@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
netfilter: Add of NATTYPE COOKIE Check

Add NATTYPE COOKIE to avoid invalid access of NATTYPE
entry from the conntrack module. This compensates for
possible garbage values in the conntrack entry, which
would cause potential errors.

Change-Id: I1a53fa0dc6961dd3e53d382642b413d4ee781ed6
Signed-off-by: Tyler Wear <twear@codeaurora.org>
Signed-off-by: Devendra Patel <cdevenp@codeaurora.org>
sdhci: sdhci_stop_request() returns error when no request

There is race between sdhci_tasklet_finish()
and sdhci_stop_request(): when the request is finished before
stop flow called, error returned.

Change-Id: Ic036feae925b2e9e5435e44f97b24a179547bf49
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
mmc: sdhci: Use max timeout and skip timeout calculation

Several data-timeout issues were seen, most of which were
due to the card taking a longer time to respond. This patch
increases the timeout of the controller to 0xF i.e. max
possible.

Change-Id: I6739de3eb5d9cccf8e39d9dc4730056782334162
CRs-Fixed: 536832
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: sdhci-msm: set core in proper mode before reset

During probe disable the HC mode since the reset is done in
SDCC mode. HC mode will get set after the reset is complete
before the rest of the initialization is done.

CRs-Fixed: 538028
Change-Id: I1fdc633c218447c15c8caad24e2805e7510088f2
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
mmc: sdhci: Add HS400 host layer support

HS400 bus speed mode also requires tuning to be performed as done in
HS200 mode. Add the capability in host layer to perform tuning for
HS400 too.

Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
mmc: sdhci-msm: Add HS400 platform support

The following msm platform specific changes are added to support HS400.
- Enable CDC calibration fixed feedback and sleep clock.
- Allow tuning for HS400 mode.
- Add capability to parse and configure pull settings for RCLK pin.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.

Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit

In HS400 mode a new RCLK is introduced on the interface for read data
transfers. The eMMC5.0 device transmits the read data to the host with
respect to rising and falling edges of RCLK. In order to ensure correct
operation of read data transfers in HS400 mode, the incoming RX data
needs to be sampled by delayed version of RCLK.

The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be
initialized, configured and enabled once during HS400 mode switch and
when operational voltage/clock is changed.

Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
mmc: sdhci-msm: enable stop transmission support

This change enables handling of urgent data transfer request by setting
MMC_CAP2_STOP_REQUEST bit of caps2 field.

In order to decrease a latency of a prioritized requests (aka Urgent
request), we might want to stop the transmission of a running "low
priority" request in order to handle the Urgent request. The urgency of
the request is decided by the block layer I/O scheduler. When the block
layer notifies the MMC layer of an urgent request and if the MMC layer is
blocked on current request to complete, it will be woken up, current
request will be stopped, any outstanding requests are reinserted back to
the block layer and urgent request execution started.

Change-Id: I542da0b2230dd8c884902f3b14c13b0744aedaa1
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
mmc: sdhci-msm: enable asynchronous interrupt support in 4-bit mode

SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off.

As SDCC driver is capable of handling the asynchronous interrupt,
advertise MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE capability.

Change-Id: Id5a86bc70b7b798b23be3a0fc0d59b2db05e0409
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
mmc: sdhci-msm: add MMC_PM_KEEP_POWER flag

This flag ensures that the power to the sdio card is not
cut-off. That way this can wake-up the device when required
using asynchronous interrupt mechanism.

Change-Id: Ic91bfdc93e117c5e627360a4d0ef80f661aa1b60
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: sdhci-msm: add USE_CORE_PM capability

Defining this capability would invoke the suspend/resume
routines defined for mmc_host device by the PM framework.

CRs-Fixed: 490021
Change-Id: I6fde407ed91f0a7249923bb156482378e2bb727c
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: sdhci: Turn on controller clocks and card power at MMC_POWER_UP

Currently, the clock to the card is enabled prior to enabling
the power to card. Specification requires that the power be
supplied first and then a delay of 10ms and then clock be
provided to the card.

In this, during MMC_POWER_UP mode, the controller clocks would be
ON and the power would be supplied to the card. In the MMC_POWER_ON
mode, the clocks to the card would be enabled and the rate set.
A callback has been provided to facilitate the enabling of
controller clocks.

CRs-Fixed: 567658
Change-Id: I2d66eae1581b9b136faaba4cafc330aeb6a3f364
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
mmc: sdhci-msm: enable controller clocks at MMC_POWER_UP

A callback to turn-on the controller clocks is implemented.
This callback would ensure that the pclk and mclk are enabled
but the output clock to the card is disabled.

CRs-Fixed: 567658
Change-Id: Ic97e600a6388fb64f1267a097b201f31d114a1fb
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
mmc: host: Use sentinels for devicetree match tables

Use sentinels as the path terminator for device match table
in drivers msm_sdcc.c and sdhci-msm.c. Without this, of_dev_lookup()
may run off the end of the array looking for bogus data.

CRs-Fixed: 582113
Change-Id: I069d3e058cea9f1bf74d48e7f7e83465ca981017
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
mmc: sdhci-msm: remove MMC_CAP_HW_RESET capability

MMC_CAP_HW_RESET capability was only referring to host driver
capability to toggle eMMC RST_n pin so if the host driver is
unable to toggle this pin, it shouldn't advertise this capability.

CRs-Fixed: 507926
Change-Id: Ia1408d95503d19ae0f7c49c7bb7905b0ddaddbd5
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

Conflicts:
	drivers/mmc/host/sdhci-msm.c
mmc: msm_sdcc: remove MMC_CAP_HW_RESET capability

MMC_CAP_HW_RESET capability was only referring to host driver
capability to toggle eMMC RST_n pin so if the host driver is
unable to toggle this pin, it shouldn't advertise this capability.

CRs-Fixed: 507926
Change-Id: Ia7b1156c6d8e8b49d69033d580e31b972124ae97
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
mmc: msm_sdcc: disable sdhci mode during probe

Now that bootloaders support sdhci mode, its possible for them
to leave the sdcc core in sdhci mode after loading the kernel
in ram and pass control to Linux for bootup. In that case if
sdcc driver was enabled, the core wont function as expected
since it happens to be in sdhci mode.

So for sdcc cores that support sdhci mode, disable SDHCi mode
before initializing the sdcc core during probe.

Change-Id: Ib9dfa7dd96d3c67979b51ea39dc4810cd44e5fd3
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
mmc: sdhci: Defer release of CPU DMA PM QoS vote in high load cases

PM QoS vote of default value mean that the CPU is allowed to move
into deepest low power mode whenever possible. Currently, if there
are back-to-back MMC requests, with a short delay, the PM QoS vote
to default value is done immediately which cause the immediate
request to have high latency as the CPU might have idle'd and moved
to deepest low power mode. To avoid this defer the PM QoS vote till
a defined timeout (pm_qos_timeout_us), so that back-to-back requests
may not suffer from additional latencies.

In addition, if the load on MMC is low, the additional latency may be
sustainable. Hence, aggressively release the vote in order to achieve
additional power savings.

CRs-Fixed: 501712
Change-Id: I82166b0ce9416eb0d519f7da26e5a96956093cb2
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
mmc: sdhci: Provide sysfs attributes to tune PM QoS unvote timeout

Provide sysfs tunables to defer PM QoS vote of default value so that
back-to-back requests wouldn't suffer from latencies caused by CPU
power collapse transition states.

Change-Id: I7180c68c1f13240faa5f432335d72e7f6b198183
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>