[X86] Teach how to dump the name of target node RDTSCP_DAG.

When I originally added node RDTSCP_DAG (r207127) I forgot to add
a string name for it in method 'getTargetNodeName'.

No functional change intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210769 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] Add bgec and bgeuc instructions
Differential Revision: http://reviews.llvm.org/D4017


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210770 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64

Summary:
To make this work for both AFGR64 and FGR64 register sets, I've had to make the
instruction definition consistent with the white lie (that it reads the lower
32-bits of the register) when they are generated by expandBuildPairF64().

Corrected the definition of hasMips32r2() and hasMips64r2() to include
MIPS32r6 and MIPS64r6.

Depends on D3956

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3957

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210771 91177308-0d34-0410-b5e6-96231b3b80d8
Don't import make_error_code into the llvm namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210772 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] Add R_MIPS_PC19_S2
Differential Revision: http://reviews.llvm.org/D3866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210773 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6

Summary: Depends on D3957

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210775 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6

Summary:
c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to
dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's
(like the GPR comparisons).

mov[fntz] have been replaced by seleqz and selnez. These instructions
conditionally zero a register based on a bool in a GPR. The results can
then be or'd together to act as a select without, for example, requiring a third
register read port.

mov[fntz].[ds] have been replaced with sel.[ds]

MIPS64r6 currently generates unnecessary sign-extensions for most selects.
This is because the result of a SETCC is currently an i32. Bits 32-63 are
undefined in i32 and the behaviour of seleqz/selnez would otherwise depend
on undefined bits. Later, we will fix this by making the result of SETCC an
i64 on MIPS64 targets.

Depends on D3958

Reviewers: jkolek, vmedic, zoran.jovanovic

Reviewed By: vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D4003

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210777 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] 80 col corrections that should have been in r210777.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210778 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6

Summary: We haven't implemented this instruction so we only add a test case.

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D4004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210779 91177308-0d34-0410-b5e6-96231b3b80d8
This removes TODO added in http://reviews.llvm.org/D3658

The patch transforms

ABS(NABS(X)) -> ABS(X)
NABS(ABS(X)) -> NABS(X)

Differential Revision: http://reviews.llvm.org/D4040



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210782 91177308-0d34-0410-b5e6-96231b3b80d8
Replace llvm::error_code with std::error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210783 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6

Summary:
Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in
mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed
by getelementptr). This does not affect the purpose of the test.

Depends on D4004

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210784 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6

Summary:
These instructions are not implemented for any MIPS ISA so we only need
testcases.

Depends on D4110

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4111

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210786 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6

Summary:
Also tightened up the acceptable condition operand for these instructions
on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior
to that only $fcc0 is acceptable.

We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's
probably best to do this in InstCombine.

Depends on D4111

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4112

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210787 91177308-0d34-0410-b5e6-96231b3b80d8
Disable the load/store optimization pass for Thumb-1.

Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out.

Patch by Moritz Roth!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210789 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors"

This reverts commit r210540, adds a testcase for the regression it
caused, and marks the R600 test it was supposed to fix as XFAIL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210792 91177308-0d34-0410-b5e6-96231b3b80d8
Remove pimpl class from PassRegistry.

Since removeRegistrationListener is no longer called during static
destruction, we can get rid of the pimpl in PassRegistry.

This should clean up the code somewhat, increase clarity, and also
allows us to put the Lock as a member of the class, instead of as a
ManagedStatic.

As part of this change, the PassInfo class is moved from
PassSupport.h to its own file, to eliminate the otherwise circular
header dependency between PassRegistry.h and PassSupport.h

Reviewed by: rnk, dblaikie

Differential Revision: http://reviews.llvm.org/D4107

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210793 91177308-0d34-0410-b5e6-96231b3b80d8
adding re-include guards into lib/Support/reg*.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210794 91177308-0d34-0410-b5e6-96231b3b80d8
Remove system_error.h.

This is a minimal change to remove the header. I will remove the occurrences
of "using std::error_code" in a followup patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210803 91177308-0d34-0410-b5e6-96231b3b80d8
Trying to fix the windows build.

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