Working front-to-back (.ap file to Verilog) codegen!

Required a number of bugfixes across the frontend and backend, the most
prominent of which were:

- binding-stack/phi-generation logic was off for both while loops and
  if/else blocks. For whiles, we were adding inputs to the header twice;
  footer phis weren't being updated. For if/else, we need to account for
  the fact that we may be deeper down the binding stack on the out-edge
  from a body if the body contained a break or continue (or 'return',
  which is desugared to a break); we need to compute the full overlay
  over multiple stack levels, as for while loops, then pop up to the
  parent's level.

  - This whole thing would be much less inscrutable (more scrutable?) if
    we generated code in another IR (proto-IR?) referring to variables
    rather than SSA valnums, then did a single reaching-definitions
    computation after all codegen to insert phis. TODO: do that.

- A few scary use-after-frees caught by valgrind. Some of these were due
  to the remove-subtrees-to-prevent-visits strategy in the codegen
  visitor pass: removing a subtree deletes it, but we may still have
  references into that subtree! Instead, the visitor abstraction allows
  handlers to return VISIT_TERMINAL now to continue the pass but prevent
  recursion into subnodes.