hdl/modules/position_nosysgen.vhd: fix wrong DDS number of points
hdl/ip_cores/general-cores: update submodule reference

For testbenches we need to have a few modules declared
only on the latest commits of general-cores repository.
hdl/modules/cic/cic_decim.v: fix wrong valid output signal

When using the CE input, the valid_o output gets asserted
only on the next clock cycle of the CE signal, causing the
following module to always miss the valid_o signal.
hdl//modules/position_nosysgen/*: remove DDS phase shift

For now, we don't use phase shifts in the DDS.
hdl/modules/dsp_cores_pkg.vhd: constraint string

Modelsim issues an error when using an unconstrained
string type in case statements. So, we contraint it
to a suitable size.
hdl/modules/position_nosysgen/*: add CE constants to ease readability
hdl/testbench/position/*: update to SIRIUS parameters
hdl/testbench/position/Manifest.py: update to AFCv3 (artix-7) board
hdl/testbench/*/position_tb.vhd: update to latest position_calc core
hdl/ip_cores/concordic: update submodule reference
hdl/ip_cores/concordic: update submodule reference
Merge branch 'multi-ce-exp' into devel