[mips][microMIPS] Implement CodeGen support for LI16 instruction.

Differential Revision: http://reviews.llvm.org/D5840


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224017 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: Added all forms of COMPRESS instruction
+ intrinsics + tests


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224019 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-ar: close input files early.

We already have them mapped into memory, so we can just close the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224020 91177308-0d34-0410-b5e6-96231b3b80d8
Only seek once before writing the member offsets.

This cuts down the number on system calls done by a static llvm-ar producing
lib/libclangSema.a from 9164 to 442.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224025 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding encoding information for sign extend word instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224026 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Ading i64 <- i32, i32 sextw pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224027 91177308-0d34-0410-b5e6-96231b3b80d8
[AVX512] Add support for 512b variable bit shift intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224028 91177308-0d34-0410-b5e6-96231b3b80d8
Remove dead code. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224029 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Implement BuildSDIVPow2, lower i64 pow2 sdiv using sradi

PPCISelDAGToDAG contained existing code to lower i32 sdiv by a power-of-2 using
srawi/addze, but did not implement the i64 case. DAGCombine now contains a
callback specifically designed for this purpose (BuildSDIVPow2), and part of
the logic has been moved to an implementation of that callback. Doing this
lowering using BuildSDIVPow2 likely does not matter, compared to handling
everything in PPCISelDAGToDAG, for the positive divisor case, but the negative
divisor case, which generates an additional negation, can potentially benefit
from additional folding from DAGCombine. Now, both the i32 and the i64 cases
have been implemented.

Fixes PR20732.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224033 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: convert isTargetIOS checks to isTargetDarwin.

The distinction is mostly useful in the front-end. By the time we get here,
there are very few situations where we actually want different behaviour for
Darwin and IOS (in fact Darwin mostly just exists in a few tests). So this
should reduce any surprising weirdness for anyone using it.

No functional change on anything anyone actually cares about.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224035 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Renaming classes in preparation for replacement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224036 91177308-0d34-0410-b5e6-96231b3b80d8
[CodeGen] Let MachineVerifierPass own its banner string

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224041 91177308-0d34-0410-b5e6-96231b3b80d8
[CodeGen] Add print and verify pass after each MachineFunctionPass by default

Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.

To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224042 91177308-0d34-0410-b5e6-96231b3b80d8
Enable machineverifier in debug mode for X86, ARM, AArch64, Mips

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224043 91177308-0d34-0410-b5e6-96231b3b80d8
Silence static analyzer warnings in LLVMSupport.

The static analyzer catches a few potential bugs in LLVMSupport. Add
in asserts to silence the warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224044 91177308-0d34-0410-b5e6-96231b3b80d8
This reverts commit r224043 and r224042.

check-llvm was failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224045 91177308-0d34-0410-b5e6-96231b3b80d8
Remove a convoluted way of calling close by moving the call to the only caller.

As a bonus we can actually check the return value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224046 91177308-0d34-0410-b5e6-96231b3b80d8
AsmParser: Don't crash on an ill-formed MDNodeVector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224053 91177308-0d34-0410-b5e6-96231b3b80d8
[InstCombine][X86] Improved folding of calls to Intrinsic::x86_sse4a_insertqi.

This patch teaches the instruction combiner how to fold a call to 'insertqi' if
the 'length field' (3rd operand) is set to zero, and if the sum between
field 'length' and 'bit index' (4th operand) is bigger than 64.

From the AMD64 Architecture Programmer's Manual:
1. If the sum of the bit index + length field is greater than 64, then the
   results are undefined;
2. A value of zero in the field length is defined as a length of 64.

This patch improves the existing combining logic for intrinsic 'insertqi'
adding extra checks to address both point 1. and point 2.

Differential Revision: http://reviews.llvm.org/D6583


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224054 91177308-0d34-0410-b5e6-96231b3b80d8
AsmParser: Don't crash on an ill-formed MDNodeVector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224056 91177308-0d34-0410-b5e6-96231b3b80d8