compiler/arm/insts: Implement disassembly of data-processing instructions.

  * The start of a working disassembler, currently able to
disassemble data-processing instructions in their various
variants.
compiler/arm/insts: Implement disassembly of relative branch instructions.

  * This is B and BL with a relative displacement, not with the
address in a register.
compiler/arm/insts: Implement disassembly of basic load/store instructions.

  * These are the word and unsigned-byte load/store instructions.
There's one bug remaining, in that the position of the byte
indicator in the instruction is incorrect when there is a
condition specified, but it's fairly minor under the circumstances.
compiler/arm/insts: Implement disassembly of SWI instructions.

  * These are the basic syscall trap instructions, which we use as
part of our pseudo-atomic exit sequence.
compiler/disassem: Create access macros for prefiltered arguments.

  * When defining an instruction format, don't limit access macros
only to those arguments which have encoded fields, also include
those which only have a prefilter (used with READ-SUFFIX, for
example).
compiler/arm/insts: Add support for decoding our debug trap and error data.

  * This is one of the nastier pieces of the ARM disassembler, and
it required changing the disassembler logic itself (the earlier
commit altering the criteria for generating an arg access macro).

  * Random things discovered while implementing this: Alpha has no
support for decoding internal-error trap codes and the like.
SNARF-ERROR-JUNK is defined virtually identically on pretty much
every platform, and whatever-CONTROL is fairly similar as well.
The only use for :CONTROL options is for trap instruction decoding.
compiler/arm/insts: Add support for status-register instructions.

  * There's a bit of cleverness here to decode the field mask for
MSR instructions, but otherwise straightforward.
Fix ARM backtrace for "escaped" frames in assembly-routines or trampolines.

  * This was two things, one of which was being able to pick out
the correct return address for when an assembly routine is active
(which is defined on a per-arch basis, but is USUALLY something to
do with an interior-pointer register), and the other of which was
compensating for using a stack slot instead of reg_LRA to pass our
LRAs around during funcall.
Fix step instrumentation on ARM.

  * A few touchpoints here.  First is the compiler backend side,
in compiler/arm/call, where we finish up the one last piece left
un-done in function calling and we add the missing VOP.  Second is
the compiler common side, where we revert stassats' changes to
disable step instrumentation.  Third is the runtime side where we
tie the trap codes emitted by the compiler into the debugger logic,
including arranging for execution to resume after the end of the
inline trap codes when returning from the trap.

  * While we're here, add a comment to arch_skip_instruction() to
explain where it is lacking as compared with other architectures.

  * And enable step.impure.lisp on ARM.
compiler/arm/insts: Implement disassembly of integer multiply instructions.

  * This is a surprisingly varied number of instructions for a
machine with no hardware divider.

  * A bit tedious to work out, but fairly straightforward by this
point.  Used separate instruction formats rather than a single
common format and a set of printer overrides for two of the three
identified multiply instruction styles.
compiler/arm/insts: Implement disassembly of the CLZ instruction.

  * Fairly simple, as it largely fits into the mould of a data
processing instruction, with several limitations on some of the
field values.  Stack a few constant field values and a printer
override, and done.
Fix PURIFY for ARM.

  * Yet another argument for having a special feature conditional
for "boxed trampoline addresses" or similar: One place in the
runtime that dealt with the difference between SPARC (and now ARM)
and everything else wasn't updated for ARM.

  * Fix FUN_RAW_ADDR_OFFSET so that ARM will PURIFY correctly.