Added option to trace with non-blocking input to the sml simulator
 Added address check for success of SC and SCD
Added address check for CSCD success
Added unpredictable behaviour assertion for sc address missmatches
Added EInstr CP0 reg 8 sel 1 holding the instruction causing an exception
Removed l3 generated sml files
Introducing a per core coherent private dcache L1
Experienced with hash functions for l1 dcache index/tag
Adding a cheri specific memory subsystem
Added cache CHERI hierarchy
Fixed L2 update in CHERI memory + log info
Refining CHERI cache hierarchy and logging info
Fixed CHERI coherence mechanism on L2 evictions
Added short tags check for L1 invalidates