msm: kgsl: Enable protected register mode for A3XX

Turn on protected register mode for the A3XX GPU family and add 0x63
(RBBM_INT_0_MASK) to the list of protected registers.

Conflicts:

        drivers/gpu/msm/adreno.h
        drivers/gpu/msm/adreno_a3xx.c

Change-Id: Ic0dedbad10ebfa6eb6d3d815b5aa9b6b6f0e8e35
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Digish Pandya <digishp@codeaurora.org>
msm: kgsl: Protect CP_STATE_DEBUG_INDEX

Put CP_STATE_DEBUG_INDEX and CP_STATE_DEBUG_DATA under protection
to keep it from being written from an IB1. Doing so however opens
up a subtle "feature" in the microcode: memory read opcodes turn off
protected mode in the microcode to do the read and then turns it
back on regardless of the initial state. This is a problem if the
memory read happens while protected mode is turned off and then we
try to access a protected register which then complains and goes boom.

To account for this irregularity explicitly turn back off protected
mode in all the places where we know this will be a problem.

Change-Id: Ic0dedbad1397ca9b80132241ac006560a615e042
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Digish Pandya <digishp@codeaurora.org>
msm: kgsl: Mark the IOMMU setstate memory as read only

Mark the IOMMU setstate memory as read only in the pagetable.

Change-Id: Ic0dedbadb19e499c749cd744c3e89be3bcb4c2a2
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Flush the UCHE when context changes

Add commands to flush the GPU UCHE when a new context submits
commands to GPU. The ensures that the new context does not use
stale data present in UCHE.

CRs-Fixed: 607976
Change-Id: I123a323be5f3fb9d1f9f96fed5bb68b8d0d27d76
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Add hang interrupt and change HW fault generation

Add a sysfs property to dynamically control HW hang interrupt.
HW fault is generated for hang interrupt only.

Conflicts:

        drivers/gpu/msm/adreno_a3xx.c

Change-Id: Ib50c57476e54cccfef0ae18a0cbb42fce29457c1
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
Signed-off-by: Digish Pandya <digishp@codeaurora.org>
msm: kgsl: Enable hang interrupt by setting right bits for A330V2

A330V2 hang interrupt bit is at a different location compared to
other A3XX cores. Set the right hang interrupt bit for A330V2.

Change-Id: I702f1653ed31907a708b19c7b2288644e2d45220
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
msm: kgsl: Fix protected mode for A3XX

Prior merges of the A3XX protected mode code were incorrect. Fix
up the changes to get the branch fully updated with the changes
from msm-3.10.

Change-Id: Ic0dedbad5a0e1aea181141de1527d74b42002e3c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Protect SMMU registers from being written by the GPU

Put the SMMU register range in protected mode to shield them from
IB1/IB2 writes from userspace.

CRs-Fixed: 599971
Change-Id: Ic0dedbad8c03fc1c54ff73221231e2440d3c34dd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>