Fix auto-comment for function/task without portlists

* verilog-mode.el (verilog-set-auto-endcomments): Detect the function-
  or task-name when auto-commenting blocks that lack an explicit
  portlist.
Add ability to auto-comment property/endproperty

* verilog-mode.el (verilog-auto-end-comment-lines-re,
  verilog-end-block-ordered-re, verilog-set-auto-endcomments): Teach
  verilog-mode to automatically comment property/endproperty blocks.
  This mimics behavior of other similar blocks like
  sequence/endsequence, function/endfunction, etc.
Relabel all lines that can be auto-commented

* verilog-mode.el (verilog-label-be): When auto-commenting a buffer,
  consider auto-comments on all known keywords (not just a subset thereof).
Add more nameable items (like endproperty: property_identifier)

* verilog-mode.el (verilog-nameable-item-re):  Teach verilog-mode about
  all nameable items, per IEEE-1800-2012.  A nameable item is one who's
  end-delimiter can be suffixed with a ": <name>".  Added items include
  endchecker, endgroup, endprogram, endproperty, and endsequence.
Auto-indent properly after `include directive, bug782

* verilog-mode.el (verilog-beg-of-statement): Teach verilog-mode to
  honor filename after `include directive, so that indentation is not
  corrupted inside certain blocks such as property/endproperty.