lib/genalloc.c: revert Huawei KGSL 'fix'

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
sched: Notify hrtimer users of switches to NOHZ mode

When NOHZ=y and high res timers are disabled (via cmdline or
Kconfig) tick_nohz_switch_to_nohz() will notify the user about
switching into NOHZ mode. Nothing is printed for the case where
HIGH_RES_TIMERS=y. Fix this for the HIGH_RES_TIMERS=y case by
duplicating the printk from the low res NOHZ path in the high res
NOHZ path.

Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
arm/smp.c: convert printk to pr_info

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
kernel/exit.c: remove Huawei kernel log spam

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
Revert "Optimized ARM RWSEM algorithm"
msm: kgsl: use kgsl_mmu_device_setstate() if the GPU is already idle

Use the default setstate function, which directly reprograms the IOMMU,
to change IOMMU pagetables or flush the TLB if the GPU is already idle.
This condition often occurs when the GPU is being powered down. In this
case it is desirable to avoid the overhead of issuing commands, waiting
for idle and firing events that results from using the GPU
command stream to reprogram the IOMMU.

Change-Id: I633002ac49c8fe58df3f1f6a1fd1ddf705fc1733
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
PM / tracing: remove deprecated power trace API

The text in Documentation said it would be removed in 2.6.41;
the text in the Kconfig said removal in the 3.1 release.  Either
way you look at it, we are well past both, so push it off a cliff.

Note that the POWER_CSTATE and the POWER_PSTATE are part of the
legacy tracing API.  Remove all tracepoints which use these flags.
As can be seen from context, most already have a trace entry via
trace_cpu_idle anyways.

Also, the cpufreq/cpufreq.c PSTATE one is actually unpaired, as
compared to the CSTATE ones which all have a clear start/stop.
As part of this, the trace_power_frequency also becomes orphaned,
so it too is deleted.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
config: *update*
msm: Remove old unused sdio related code

Cleanup mach-msm by removing unused sdio related code.

Change-Id: I485deb7d6499771294b494f5542ba510c10255cb
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
msm: Remove ANDROID_PMEM from the Kconfig dependencies

The PMEM driver is completely deprecated. Remove any Kconfig
that is still depending on it.

Change-Id: I3386a7eedf34213f2c644372a719ae00c65b0d6d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
msm: avs: Remove vestigial software based AVS

Older targets like 8x50 had the first version of Apdaptive Voltage
Scaling done in software. This feature was never enabled and supported.
Remove the code and the associated config items.

Change-Id: If3bdab7d0bdb5d51e099f7c37f56592826edc102
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
msm: event_timer: Support to add event timers.

Add support to allow drivers to specify future events
that need to be treated as hard deadlines. Upon event timer
expiry the driver will be notified by callback function
that the driver provides.
The pm code can query the earliest event and modify
the event timer accounting for the back off based on the
latency of the low power mode being entered.

Change-Id: Iec26f77de3b826bff456b12f3230268d9bdc2255
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
msm: Rename pmem variables and macros

Since MSM no longer uses PMEM, the variables, macros, and kernel
config (CONFIG_KERNEL_PMEM_EBI_REGION) relating to PMEM should be
renamed to something more generic.

Change-Id: I4ca909098c96317853d4f040850b63f37db4811e
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Revert: genirq: explicitly mask a freed irq

This reverts:

      When an interrupt is freed, the shutdown or the disable callback
      is called for that interrupt. These calls might not be implemented
      or even if they were, might not mask the interrupt.

      Explicitly mask the interrupt when it is freed. If not masked, the
      interrupt could trigger, set the pending bit in the irq controller
      and cause unnecessary wakeup or exits from idle power collapse.

      Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Revert: genirq: chip: set pending only for edge interrupts

This reverts:

      The IRQS_PENDING flag is meant to record an edge interrupt trigger event
      when that interrupt is disabled.

      When an edge triggered interrupt is enabled, check_irq_resend() retriggers
      that irq and resets the flag to zero if set. Note that check_irq_resend()
      only does this for edge triggered interrupts.

      For level triggered interrupts it is expected that the interrupt remains
      active and doesn't need this PENDING flag assistance from software for
      re-triggering it.

      However, handle_fasteoi_irq flow handler sets the PENDING flag even for
      a disabled level interrupt. This causes an adverse effect if that level
      interrupt is marked wakeup. The suspend code sees the pending flag on a
      wakeup interrupt and aborts suspend whereas check_irq_resend does not reset
      it to 0 (as it is a level interrupt). The end result is that the PENDING
      flag on this level triggered wakeup interrupt never clears and the system
      keeps aborting suspend.

      Fix this by setting IRQS_PENDING flag only for edge interrupts in the
      handle_fasteoi_irq.

      CRs-Fixed: 314344
      Change-Id: I775d40f434f9309fd9672bae372b0f0fb5b91627
      Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Revert: genirq: fix handle_nested_irq for lazy disable

This reverts:

      When lazy disabling is implemented and an interrupt is disabled the
      genirq code ends up marking it as IRQ_DISABLED in the descriptor.
      The interrupt stays enabled in the controller.  If the interrupt
      fires after disabling, the flow handlers namely handle_level_irq and
      handle_edge_irq mask the interrupt in the controller.

      This is not the case with handle_nested_irq. The interrupt stays enabled in
      the controller and if it were a level interrupt it keeps firing only to be
      ignored by handle_nested_irq.

      Update handle_nested_irq to mask such an interrupt.

      CRs-Fixed: 300931
      Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
ARM: hw_breakpoint: *squashing updates*

ARM: hw_breakpoint: enable HAVE_HW_BREAKPOINT feature flag

      HAVE_HW_BREAKPOINT was disabled temporarily from commit
      480a82f59712136b51ee5ca05c4f22c1738010c5. Issue not seen with the
      latest kernel hence re-enable the feature and fix merge issue from
      previous kernel upgrade.

ARM/hw_breakpoint: upstream mainline

ARM: 7496/1: hw_breakpoint: don't rely on dfsr to show watchpoint access type

      From ARM debug architecture v7.1 onwards, a watchpoint exception causes
      the DFAR to be updated with the faulting data address. However, DFSR.WnR
      takes an UNKNOWN value and therefore cannot be used in general to
      determine the access type that triggered the watchpoint.

      This patch forbids watchpoints without an overflow handler from
      specifying a specific access type (load/store). Those with overflow
      handlers must be able to handle false positives potentially triggered by
      a watchpoint of a different access type on the same address. For
      SIGTRAP-based handlers (i.e. ptrace), this should have no impact.

ARM: 7497/1: hw_breakpoint: allow single-byte watchpoints on all addresses

      Breakpoint validation currently fails for single-byte watchpoints on
      addresses ending in 11b. There is no reason to forbid such a watchpoint,
      so extend the validation code to allow it.

ARM: hw_breakpoint: only clear OS lock when implemented on v7

      The OS save and restore register are optional in debug architecture v7,
      so check the status register before attempting to clear the OS lock.

ARM: hw_breakpoint: fix monitor mode detection with v7.1

      Detecting whether halting debug is enabled is no longer possible via
      the DBGDSCR in v7.1, returning an UNKNOWN value for the HDBGen bit via
      CP14 when the OS lock is clear.

      This patch removes the halting mode check and ensures that accesses to
      the internal and external views of the DBGDSCR are serialised with an
      instruction barrier.

ARM: hw_breakpoint: fix ordering of debug register reset sequence

      The debug register reset sequence for v7 and v7.1 is congruent with
      tap-dancing through a minefield.

      Rather than wait until we've blown ourselves to pieces, this patch
      instead checks the debug_err_mask after each potentially faulting
      operation. We also move the enabling of monitor_mode to the end of the
      sequence in order to prevent spurious debug events generated by UNKNOWN
      register values.

ARM: hw_breakpoint: don't try to clear v6 debug registers during boot

      v6 cores do not provide a way to clear the debug registers without first
      enabling monitor mode, meaning that we could take spurious debug
      exceptions. Instead, rely on the registers being in a sane state when we
      boot as they are defined to be disabled out of reset anyway.

ARM: hw_breakpoint: make boot quieter without CPUID feature registers

      Booting on a v6 core without the CPUID feature registers (e.g. 1136)
      leads to a noisy dmesg complaining about their absence.

      This patch changes the pr_warning into a pr_warn_once to keep the log
      quieter.

ARM: hw_breakpoint: check if monitor mode is enabled during validation

      Rather than attempt to enable monitor mode explicitly when scheduling in
      a breakpoint event (which could raise an undefined exception trap when
      accessing DBGDSCRext), instead check that DBGDSCRint.MDBGen is set
      during event validation and report an error to the caller if not.

ARM: hw_breakpoint: use CRn as argument for debug reg accessor macros

      The coprocessor register CRn for accesses to the debug register can be a
      different one than C0. Take this into account for the ARM_DBG_READ and
      the ARM_DBG_WRITE macro.

      The inline assembler calls which used a coprocessor register CRn other
      than C0 are replaced by the ARM_DBG_READ or ARM_DBG_WRITE macro.

ARM: hw_breakpoint: kill WARN_ONCE usage

      WARN_ONCE is a bit OTT for some of the simple failure cases encountered
      in hw_breakpoint, so use either pr_warning or pr_warn_once instead.

ARM: hw_breakpoint: Check function for OS Save and Restore mechanism

      v7 debug introduced OS Save and Restore mechanism. On a v7 debug SinglePower
      system, i.e a system without a separate core and debug power domain, which does
      not support external debug over powerdown, it is implementation defined whether
      OS Save and Restore is implemented.
      v7.1 debug requires OS Save and Restore mechanism. v6 debug and v6.1 debug do
      not implement it.

      A new global variable bool has_ossr is introduced and is determined in
      arch_hw_breakpoint_init() like debug_arch or the number of BRPs/WRPs.

      The logic how to check if OS Save and Restore is supported has changed with
      this patch. In reset_ctrl_regs() a mask consisting of OSLM[1] (OSLSR.3) and
      OSLM[0] (OSLSR.0) was used to check if the system supports OS Save and
      Restore. In the new function core_has_os_save_restore() only OSLM[0] is used.
      It is not necessary to check OSLM[1] too since it is v7.1 debug specific and
      v7.1 debug requires OS Save and Restore and thus OS Lock.

ARM: hw_breakpoint: Debug powerdown support for self-hosted debug

      This patch introduces debug powerdown support for self-hosted debug for v7
      and v7.1 debug architecture for a SinglePower system, i.e. a system without a
      separate core and debug power domain. On a SinglePower system the OS Lock is
      lost over a powerdown.

      If CONFIG_CPU_PM is set the new function pm_init() registers hw_breakpoint
      with CPU PM for a system supporting OS Save and Restore.

      Receiving a CPU PM EXIT notifier indicates that a single CPU has exited a low
      power state. A call to reset_ctrl_regs() is hooked into the CPU PM EXIT
      notifier chain. This function makes sure that the sticky power-down is clear
      (only v7 debug), the OS Double Lock is clear (only v7.1 debug) and it clears
      the OS Lock for v7 debug (for a system supporting OS Save and Restore) and
      v7.1 debug. Furthermore, it clears any vector-catch events and all
      breakpoint/watchpoint control/value registers for v7 and v7.1 debug.

ARM: 7662/1: hw_breakpoint: reset debug logic on secondary CPUs in s2ram resume

      We must mask out the CPU_TASKS_FROZEN bit so that reset_ctrl_regs is
      also called on a secondary CPU during s2ram resume, where only the boot
      CPU will receive the PM_EXIT notification.

ARM: 7681/1: hw_breakpoint: use warn_once to avoid spam from reset_ctrl_regs()

      CPU debug features like hardware break, watchpoints can be used only
      when the debug mode is enabled and available. Unfortunately on OMAP4
      based devices, after a CPU power cycle, the debug feature gets disabled
      which leads to a flood of messages coming from reset_ctrl_regs() which
      gets called on every CPU_PM_EXIT with CPUidle enabled.

      So make use of warn_once() so that system is usable.

      Thanks to Will for pointers and Lokesh for the analysis of the issue.

ARM: 7697/1: hw_breakpoint: do not use __cpuinitdata for dbg_cpu_pm_nb

      We must not declare dbg_cpu_pm_nb as __cpuinitdata as we need it after
      system initialization for Suspend and CPUIdle.

      This was done in commit 9a6eb310eaa5 ("ARM: hw_breakpoint: Debug powerdown
      support for self-hosted debug").

Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
lockdep, rwsem: provide down_write_nest_lock()

      down_write_nest_lock() provides a means to annotate locking scenario
      where an outer lock is guaranteed to serialize the order nested locks
      are being acquired.

      This is analogoue to already existing mutex_lock_nest_lock() and
      spin_lock_nest_lock().

      Signed-off-by: Jiri Kosina <jkosina@suse.cz>
      Cc: Rik van Riel <riel@redhat.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mel Gorman <mel@csn.ul.ie>
      Tested-by: Sedat Dilek <sedat.dilek@gmail.com>
      Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
      Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

lockdep, rwsem: fix down_write_nest_lock() if !CONFIG_DEBUG_LOCK_ALLOC

      Commit 1b963c81b145 ("lockdep, rwsem: provide down_write_nest_lock()")
      contains a bug in a codepath when CONFIG_DEBUG_LOCK_ALLOC is disabled,
      which causes down_read() to be called instead of down_write() by mistake
      on such configurations.  Fix that.

      Reported-and-tested-by: Andrew Clayton <andrew@digital-domain.net>
      Reported-and-tested-by: Zlatko Calusic <zlatko.calusic@iskon.hr>
      Signed-off-by: Jiri Kosina <jkosina@suse.cz>
      Reviewed-by: Rik van Riel <riel@redhat.com>
      Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Revert "rw_semaphore: remove up/down_read_non_owner"

This reverts commit 11b80f459adaf91a712f95e7734a17655a36bf30.

Bcache needs rw semaphores for cache coherency in writeback mode -
writes have to take a read lock on a per cache device rw sem, and
release it when the bio completes.

But since this is for bios it's naturally not in the context of the
process that originally took the lock.

Signed-off-by: Kent Overstreet <koverstreet@google.com>
CC: Christoph Hellwig <hch@infradead.org>
CC: David Howells <dhowells@redhat.com>