hlte: rollback ion

Revert "staging: ion: Add GFP_NO_KSWAPD flag to high order allocations"

This reverts commit 34a28f93e64f80d6f6bd5bf945a0f48e09957540.

Revert "staging: ion: Add source of allocated page"

This reverts commit 62ade932eb5446df02c9e3c58b4b3f9439779ef9.

Revert "ion: fix remaining instances of sg_dma_len"

This reverts commit c5b0de72b0f7262439d9de0ea7c4feca427e2aab.

Revert "ion: cma_secure_heap: validate buffer length"

This reverts commit cc3fb1311b46eff8eac26ee4e5a9a15fc13d9a01.

Revert "ion: secure_buffer: fix iteration of sg_table"

This reverts commit 781868c7b1fa6a9879a524e7e44cec04256013f2.

Revert "staging: ion: msm: Only parse available dt nodes"

This reverts commit e6a2b7c49638a41d5fa1dc8d65a324d038244a6a.

Revert "ion: Squashed commit of upstream updates"

This reverts commit 1ec369a25dac64764f62cbd36679651c34007a52.

Revert "ion: chunk_heap: fix leak in allocated counter"

This reverts commit c9507092ef39f130ee82e70b645cbd432e8ec3d9.

Revert "ion: remove use of qcom,msm-ion-reserve"

This reverts commit 88821715e2eb6aeb43c7e7f9277f1a58600d919d.

Revert "ion: remove ion_cp_heap"

This reverts commit 0bf5daa1f8f958b0547f65f3697b14c3327eb6dd.

Revert "ARM: dts: msm: Migrate 8x74 memory regions to CMA"

This reverts commit 1e352aac30dacedd2ffe72ce08f4425df425200c.

Revert "msm8974: Update Samsung DT with new memory layout"

This reverts commit 0c342f35f6a0afad5338b9956e927464c787cbe4.

Revert "ion: use PAGE_KERNEL instead of pgprot_kernel"

This reverts commit 9a9efd25fb2a285cb0e18d6236269e206f14e270.

Revert "ion: use iounmap instead of __arm_iounmap"

This reverts commit 8744a1d2040f83643e59953587b6b50d7a8ed1a6.

Conflicts:
	arch/arm/mach-msm/board-8974.c
	arch/arm/mach-msm/include/mach/memory.h
ion: Add missing unlock on error path

A mutex_unlock was missing for the alloc_lock on an error
path. Add it.

Change-Id: If88b72fbc2fd18504347b784d5daa2bc9170c55f
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
ion: retry during race with shrinking/allocating

There exists a race between shrinking/allocating

Thread 1:                           Thread:2
mutex_lock(&sheap->alloc_lock)
ion_secure_cma_add_to_pool()
mutex_lock(&sheap->chunk_lock)
chunk->cnt = 0
mutex_unlock(&sheap->chunk_lock)
                                    ion_secure_cma_shrinker
                                    mutex_lock(&sheap->chunk_lock)
                                    __ion_secure_cma_shrink_pool
                                    chunk->cnt == 0 for the
                                       just allocated chunk
                                    ion_secure_cma-free_chunk
ion_secure_cma_alloc_from_pool
no memory to allocate!

If this race happens, just retry adding memory to the pool instead
of BUGing out the system.

Change-Id: Ic95782db6d88a33f01dcc5248fc957ca0f378078
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
cpufreq: Unified governor/scaling switching (squashed commits)

cpufreq: unified governor and scaling min and max switching governor scaling_min_freq and scaling_max_freq will be populated to all online cpus immediately

cpufreq: unified governor and scaling min and max switching use related_cpus to apply correctly to new online cpus

cpufreq: block hotplugging during multi-cpu operations

cpufreq: dont apply multi-cpu values if not changed

Change-Id: I199d47409d1ed15bbf9e4856d528344560c6f092

Conflicts:
	drivers/cpufreq/cpufreq.c
msm8974: cpufreq: Fix broken uevents for cpufreq governor and cpu devices

Change-Id: I906da5f2183467f3ec7e1e11595199e29e90c1ca
[1/2] find7: cpuquiet: initial bringup

Adds also required load average API in scheduler
Make sure you have disabled mpdecision if you use this

PS2:
-added enabled sysfs to allow easy disabling if required
-disable mpdecision load calc code if cpuquiet is running

Change-Id: I622fbc3027df897c380c51befc6da4f5bad39b2e

Conflicts:
	drivers/Kconfig
	drivers/Makefile
enable cpuquiet
enable hotplug
msm8974: added input mediator

Brain dumb simple 2 level input event chain.
For clients that want input events to appear in a
certain order e.g. cpu hotplugging should get it
before cpufreq so that input boost is on all online
cpus

This is used in load_stats and rq_stats hotplugging
governor and in smartmax cpu governor

This is completely optional and will not influence
"normal" input event handling

Change-Id: I3e3c28cffb640ec0f543eea7994a55bfa4182221
enable input mediator
cpufreq: Fix wrong location of mutex_unlock in conservative

Change-Id: Idb1077c667cced6ff87add82afdcfbf08696aaa2
PM: devfreq: Fix simple_ondemand crashing on startup

simple_ondemands private data must be set to NULL, otherwise we would
run into a NULL pointer in kgsl_devfreq_get_dev_status().

Change-Id: I6cc6a8b11e3b58b8c3e3c26d43ee36949cf62351
cpufreq: ondemand: Stop kernel threads on governor stop

stop wasting useless cpu cycles if disabled

Change-Id: I6e5fa3f0c3fc0f86ea5f94e17a05de3f90db3057

Conflicts:
	drivers/cpufreq/cpufreq_ondemand.c
msm8974: cpufreq: disable cpu iterating for scaling limit

Change-Id: I366a7052b77e99858f0ab1e3f8a7068b447a6d74
cpufreq: overall_stats: add overall stats for all available cores

this is much more accurate stats tracking than just displaying core 0's
stats from most other kernels

Signed-off-by: faux123 <reioux@gmail.com>

overall_stats: make dual/quad core stats configurable via meunconfig

Signed-off-by: faux123 <reioux@gmail.com>

overall_stats: forward port to kernel 3.4+

by replacing deprecated functions with native add/sub for 64bit data types

Change-Id: I1e17d626bf59b3c0822c9f1088093f848fd2649c
Signed-off-by: faux123 <reioux@gmail.com>
Conflicts:
	drivers/cpufreq/Kconfig
enable overall stats
ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+

The open-coded mutex implementation for ARMv6+ cores suffers from a
severe lack of barriers, so in the uncontended case we don't actually
protect any accesses performed during the critical section.

Furthermore, the code is largely a duplication of the ARMv6+ atomic_dec
code but optimised to remove a branch instruction, as the mutex fastpath
was previously inlined. Now that this is executed out-of-line, we can
reuse the atomic access code for the locking (in fact, we use the xchg
code as this produces shorter critical sections).

This patch uses the generic xchg based implementation for mutexes on
ARMv6+, which introduces barriers to the lock/unlock operations and also
has the benefit of removing a fair amount of inline assembly code.

Cc: <stable@vger.kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reported-by: Shan Kang <kangshan0910@gmail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

mutex: Place lock in contended state after fastpath_lock failure

ARM recently moved to asm-generic/mutex-xchg.h for its mutex
implementation after the previous implementation was found to be missing
some crucial memory barriers. However, this has revealed some problems
running hackbench on SMP platforms due to the way in which the
MUTEX_SPIN_ON_OWNER code operates.

The symptoms are that a bunch of hackbench tasks are left waiting on an
unlocked mutex and therefore never get woken up to claim it. This boils
down to the following sequence of events:

        Task A        Task B        Task C        Lock value
0                                                     1
1       lock()                                        0
2                     lock()                          0
3                     spin(A)                         0
4       unlock()                                      1
5                                   lock()            0
6                     cmpxchg(1,0)                    0
7                     contended()                    -1
8       lock()                                        0
9       spin(C)                                       0
10                                  unlock()          1
11      cmpxchg(1,0)                                  0
12      unlock()                                      1

At this point, the lock is unlocked, but Task B is in an uninterruptible
sleep with nobody to wake it up.

This patch fixes the problem by ensuring we put the lock into the
contended state if we fail to acquire it on the fastpath, ensuring that
any blocked waiters are woken up when the mutex is released.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Chris Mason <chris.mason@fusionio.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: <stable@vger.kernel.org>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/n/tip-6e9lrw2avczr0617fzl5vqb8@git.kernel.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

ARM: 7495/1: mutex: use generic atomic_dec-based implementation for ARMv6+

Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based
implementation for ARMv6+") removed the barrier-less, ARM-specific
mutex implementation in favour of the generic xchg-based code.

Since then, a bug was uncovered in the xchg code when running on SMP
platforms, due to interactions between the locking paths and the
MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place
lock in contended state after fastpath_lock failure"), however, the
atomic_dec-based mutex algorithm is now marginally more efficient for
ARM (~0.5% improvement in hackbench scores on dual A15).

This patch moves ARMv6+ platforms to the atomic_dec-based mutex code.

Change-Id: I6621bcd491a75f75aa6e75adffc7e47d3632c6e6
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arm/crypto: Add optimized AES and SHA1 routines

Add assembler versions of AES and SHA1 for ARM platforms.  This has provided
up to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1.

Platform   CPU SPeed    Endian   Before (bps)   After (bps)   Improvement

IXP425      533 MHz      big     11217042        15566294        ~38%
KS8695      166 MHz     little    3828549         5795373        ~51%

Signed-off-by: David McCullough <ucdevel@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

ARM: 7626/1: arm/crypto: Make asm SHA-1 and AES code Thumb-2 compatible

This patch fixes aes-armv4.S and sha1-armv4-large.S to work
natively in Thumb.  This allows ARM/Thumb interworking workarounds
to be removed.

I also take the opportunity to convert some explicit assembler
directives for exported functions to the standard
ENTRY()/ENDPROC().

For the code itself:

  * In sha1_block_data_order, use of TEQ with sp is deprecated in
    ARMv7 and not supported in Thumb.  For the branches back to
    .L_00_15 and .L_40_59, the TEQ is converted to a CMP, under the
    assumption that clobbering the C flag here will not cause
    incorrect behaviour.

    For the first branch back to .L_20_39_or_60_79 the C flag is
    important, so sp is moved temporarily into another register so
    that TEQ can be used for the comparison.

  * In the AES code, most forms of register-indexed addressing with
    shifts and rotates are not permitted for loads and stores in
    Thumb, so the address calculation is done using a separate
    instruction for the Thumb case.

The resulting code is unlikely to be optimally scheduled, but it
should not have a large impact given the overall size of the code.
I haven't run any benchmarks.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Tested-by: David McCullough <ucdevel@gmail.com> (ARM only)
Acked-by: David McCullough <ucdevel@gmail.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7723/1: crypto: sha1-armv4-large.S: fix SP handling

Make the SHA1 asm code ABI conformant by making sure all stack
accesses occur above the stack pointer.

Origin:
http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7837/3: fix Thumb-2 bug in AES assembler code

commit 40190c85f427dcfdbab5dbef4ffd2510d649da1f upstream.

Patch 638591c enabled building the AES assembler code in Thumb2 mode.
However, this code used arithmetic involving PC rather than adr{l}
instructions to generate PC-relative references to the lookup tables,
and this needs to take into account the different PC offset when
running in Thumb mode.

Change-Id: I0d036eaa94dabefa0a025d522f415c663d00ae9f
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
enable optimized AES and SHA1 routines
fix derp