Fix timer overflow code.

Teensy doesn't need to worry about overflows since all of
its timers are only 16-bit.

For PWM, the pulse width needs to be able to vary from 0..period+1
(pulse-width == period+1 corresponds to 100% PWM)

I couldn't test the 0xffffffff cases since we can't currently get a
period that big in python. With a prescaler of 0, that corresponds
to a freq of 0.039 (i.e. cycle every 25.56 seconds), and we can't
set that using freq or period.

I also tested both stmhal and teensy with floats disabled, which
required a few other code changes to compile.
teensy: Enable 8-byte stack alignment for IRQ Handlers.
Added pyb.elapsed_millis and pyb.elapsed_micros

tested using:
stmhal: https://github.com/dhylands/upy-examples/blob/master/elapsed.py
teensy: https://github.com/dhylands/upy-examples/blob/master/teensy/elapsed.py
Merge pull request #877 from dhylands/timer-overflow

Fix timer overflow code.
Merge pull request #878 from bvernoux/master

Fix error: unknown type name 'size_t'
Merge pull request #880 from dhylands/irq-align

teensy: Enable 8-byte stack alignment for IRQ Handlers.
Merge pull request #881 from dhylands/elapsed

Added pyb.elapsed_millis and pyb.elapsed_micros
stmhal: Fix edge case for timer PWM of 100%.

Also improve precision of calculating PWM percent in integer mode.
Also update teensy with edge case fix.
stmhal: Add label to internal flash drive on creation.
stmhal, fatfs: Use stdlib for string fns; make all private fns static.

We save some code bytes by using builtin string functions.