ARM64: fix SELECT_CC lowering in absence of NaNs.

We were swapping the true & false results while testing for FMAX/FMIN,
but not putting them back to the original state if the later checks
failed.

Should fix PR19700.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208469 91177308-0d34-0410-b5e6-96231b3b80d8
SCEV: Use range-based for loop and fold variable into assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208476 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Use pseudo instruction for fabs/clamp/fneg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208478 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Prettier display of input modifiers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208479 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fold fabs/fneg into src input modifier

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed a bug when lowering build_vector (PR19694)

When lowering build_vector to an insertps, we would still lower it, even
if the source vectors weren't v4x32. This would break on avx if the source
was a v8x32. We now check the type of the source vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208487 91177308-0d34-0410-b5e6-96231b3b80d8
Reorder shuffle and binary operation.

This patch enables transformations:

    BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2))
    BinOp(shuffle(v1), const1) -> shuffle(BinOp, const2)

They allow to eliminate extra shuffles in some cases.

Differential Revision: http://reviews.llvm.org/D3525


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208488 91177308-0d34-0410-b5e6-96231b3b80d8
[llvm-readobj] Print values of FLAGS and MIPS_FLAGS dynamic table tags
in a human readable form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208489 91177308-0d34-0410-b5e6-96231b3b80d8
SLPVectorizer: Instead of just performing CSE on dead blocks ignore them completely.

Turns out that there is a very cheap way of testing whether a block is dead,
just look it up in the DomTree. We have to do this anyways so just ignore
unreachable blocks before sorting by domination. This restores a proper
ordering for std::stable_sort when dead code is present.

Covered by existing tests & buildbots running in STL debug mode (MSVC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208492 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: Simplify constant value emission.

This code looks to have become dead at some time in the past. I tried to
reproduce cases where LLVM would emit constants with dataN, but could
not. Upon inspection it seems the code doesn't do that anymore - the
only time a size is provided by isTypeSigned is when the type is signed,
and in those cases we use sdata. dataN is only used for unsigned types
and isTypeSigned doesn't provide a value for sizeInBits in that case.

Remove the dead cases/size plumbing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208494 91177308-0d34-0410-b5e6-96231b3b80d8
DwarfUnit: Share common constant value emission between APInts of small (<= 64 bit) and MCOperand immediates.

Doesn't seem a good reason to duplicate this code (it was more literally
duplicated prior to r208494, and while the dataN code /does/ actually
fire in this case, it doesn't seem necessary (and the DWARF standard
recommends using udata/sdata pervasively instead of dataN, so as to
indicate signedness of the values))

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208495 91177308-0d34-0410-b5e6-96231b3b80d8
DwarfUnit: Factor out calling isUnsignedDIType into a utility function so each caller of emitConstantValue doesn't have to call it separately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208496 91177308-0d34-0410-b5e6-96231b3b80d8
DwarfUnit: Pick a winner between isTypeSigned and isUnsignedDIType.

And the winner by a nose is isUnsignedDIType, for no particular reason.

These two functions were just complements of each other and used in very
related code, so refactor callers to just use one of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208500 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] On PPC32, 128-bit shifts might be runtime calls

The counter-loops formation pass needs to know what operations might be
function calls (because they can't appear in counter-based loops). On PPC32,
128-bit shifts might be runtime calls (even though you can't use __int128 on
PPC32, it seems that SROA might form them).

Fixes PR19709.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208501 91177308-0d34-0410-b5e6-96231b3b80d8
DwarfUnit: Make explicit a limitation/bug in enumeration constant emission.

Filed as PR19712, LLVM fails to detect the right type of an enum
constant when a frontend does not provide an underlying type for the
enumeration type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208502 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: Simplify/correct test for correct constant emission when dealing with derived types.

This test was using the inliner and other optimizations to test a case
that's actually a bug anyway. Bug and possible fix/discussion described
here ( http://reviews.llvm.org/D3714 ).

But the functionality that was implemented along with this test is still
desired, so simplify the test to verify a more obvious/less wrong case
that the functionality addressed: looking through const sugar to the
underlying type when emitting a constant (so the constant is emitted as
signed/unsigned as appropriate depending on the signedness of the
underlying type).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208504 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: Include lexical scopes in inlined subroutines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208506 91177308-0d34-0410-b5e6-96231b3b80d8
Add 'override' to getRegisterByName in *ISelLowering.h

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208507 91177308-0d34-0410-b5e6-96231b3b80d8
Pass the value type to TLI::getRegisterByName

We must validate the value type in TLI::getRegisterByName, because if we
don't and the wrong type was used with the IR intrinsic, then we'll assert
(because we won't be able to find a valid register class with which to
construct the requested copy operation). For PPC64, additionally, the type
information is necessary to decide between the 64-bit register and the 32-bit
subregister.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208508 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Add global named register support

Support for the intrinsics that read from and write to global named registers
is added for r1, r2 and r13 (depending on the subtarget).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208509 91177308-0d34-0410-b5e6-96231b3b80d8