Fixed so that simulation can run even with X inputs, no need to force initial condition, logic stabilises when output is determined. Depending on logic function, output can be defined even if some inputs are X.

Tests with real verilog simulators shows that with a forced unstable initial condition, such as q = _q = 1 on a RS latch, the simulator gets locked up with infinite state transitions, so the locked state does not have to be handled by the simulator.