hdl: ATSC TX FPGA Implementation

A FPGA based ATSC transmitter to offload the pilot insertion, filtering and shift to baseband.  Using the bladeRF-cli load the atsc_tx fpga image.  This image anticipates atsc symbols(0-7) written down in 32-bit words, with each word containing 8 4-bit symbols.  Symbols in a word are transmitted starting with the lowest nibble and increasing until all are consumed.

Launching the image on channel 14-1 can be achieved with the following commands:

set frequency 473000000
set samplerate 32286713.2867

set txvga1 -4
set txvga2 20

tx config file=XXXX repeat=0 delay=0
tx start

where XXXX is the properly formatted ATSC symbol file.

hdl: cleanup bad comments, remove unused signals.

hdl: atsc tx cleanup.

hdl: fix whitespace error in build script

hdl: Fix a bug in bit shifter, correct the pilot scaling

hdl: change symbol width sent over USB from 3 bits to 4, correct centering tone

hdl: Include new fx3 pll, update top level to use it
bladeRF-cli: Add raw file format format type.