i965: Set Line Width correctly on Cherryview and Skylake.

Line Width moved to DW1 bits 29:12.  It's actually now a U11.7.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965: Use ctx->Const.MaxLineWidth when clamping ctx->Line.Width.

Rather than hardcoding platform values in every code path, just use the
maximum value we set.

Currently, ctx->Const.LineWidth == 5, which is smaller than the hardware
limit.  But applications shouldn't be using a value larger than we
support anyway.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965: Advertise larger line widths.

We've artificially been limiting this to 5 for no particular reason.

On Gen4-5, the limit is [0, 7.5] with a granularity of 0.5 (U3.1).
On Gen6+, the limit is [0, 7.9921875].  Since it's a U3.7, the
granularity should be 0.125 (1/8).

This patch conservatively advertises one granularity smaller than the
hardware's maximum value, just in case there's a problem using the
largest possible value.  On Gen4-5, this is 7.5 - 0.5 = 7.0.  On Gen6+,
this is 8.0 - 0.125 = 7.875.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965: Advertise a line width of 40.0 on Cherryview and Skylake.

According to the documentation, line widths higher than 40.0 may have
quality problems.  That's already 20 times larger than we've been
exposing, so it seems totally sufficient.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>