[X86] Remove unnecessary 'In64BitMode' predicate for instructions that already indicate use of REX.W.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224495 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Don't use PS prefix on LDMXCSR/STMXCSR.

Near as I can tell prefixes are ignored on these instructions except for a comment in the Intel docs about 0xf3. Binutils disassembler seems to ignore prefixes on these instructions. Our disassembler still doesn't distinguish PS and "no prefix" well enough for this to make a functional change, but it helps with experiments I'm doing on a potential new disassembler table builder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224496 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Use correct opsize on indirect call and jump aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224497 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Use MCPhysReg for tables of registers. Const-correct the tables. Only put the anonymous namespace around classes. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224498 91177308-0d34-0410-b5e6-96231b3b80d8
Modernize the getStreamedBitcodeModule interface a bit. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224499 91177308-0d34-0410-b5e6-96231b3b80d8
[SROA] Cleanup - remove the use of std::mem_fun_ref nonsense and use
a lambda now that we have them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224500 91177308-0d34-0410-b5e6-96231b3b80d8
test: avoid unnecessary temporary files

Use pipes and redirect the error output to FileCheck directly.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224501 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: improve instruction validation for thumb mode

The ARM Architecture Reference Manual states the following:
  LDM{,IA,DB}:
    The SP cannot be in the list.
    The PC can be in the list.
    If the PC is in the list:
      • the LR must not be in the list
      • the instruction must be either outside any IT block, or the last
        instruction in an IT block.
  POP:
    The PC can be in the list.
    If the PC is in the list:
      • the LR must not be in the list
      • the instruction must be either outside any IT block, or the last
        instruction in an IT block.
  PUSH:
    The SP and PC can be in the list in ARM instructions, but not in Thumb
    instructions.
  STM:{,IA,DB}:
    The SP and PC can be in the list in ARM instructions, but not in Thumb
    instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224502 91177308-0d34-0410-b5e6-96231b3b80d8