Rejigger clocking to hold phase lock between memory controller and primary/secondary logic clocks
Hold design in effective reset until DCMs have stabilized and memory controller has fully initialized
Hold memory controller in effective reset until MCB has finished calibration and DCMs have locked
Add simple module to initialize the memory space to a known value for debugging purposes
Move division modules into blob extractor
Minor syntatical cleanup of various modules
Disabled almost all memory controller optimizations for debug.  Needs work to increase speed!