untested chgs of add_mul_sim in add_mul which generates verilog and vhdl
waveletsim now is using add_mul_sim in pass 0 & pass 1 for both fwd and res
adding a program to compute  mse_max_png
16,6
mse =  0.0684967041016
max =  67.0
16,8
mse =  0.0
max =  121.0
16,9
mse =  0.0
max =  1.0
15,9
mse =  0.0
max =  1.0
16,10
mse =  0.0
max =  1.0

add_mul_sim used in both pass 0 and pass1
16,10
mse =  1.52587890625e-05
max =  2.0

mse =  1.52587890625e-05
max =  2.0