SelectionDAG: Expand SELECT_CC to SELECT + SETCC

This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors

This prevents a future commit from regressing:

test/CodeGen/R600/setcc-equivalent.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210540 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC

The SelectionDAG bad a special case for ISD::SELECT_CC, where it would
allow targets to specify:

setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);

to indicate that they wanted to expand ISD::SELECT_CC for all types.
This wasn't applied correctly everywhere, and it makes writing new
DAG patterns with ISD::SELECT_CC difficult.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210541 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bug in the Thumb1 ARM Load/Store optimizer

Previously, the basic block was searched for future uses of the base register,
and if necessary any writeback to the base register was reset using a SUB
instruction (e.g. before calling a function) just before such a use. However,
this step happened *before* the merged LDM/STM instruction was built. So if
there was (e.g.) a function call directly after the not-yet-formed LDM/STM,
the pass would first insert a SUB instruction to reset the base register,
and then (at the same location, incorrectly) insert the LDM/STM itself.

This patch fixes PR19972. Patch by Moritz Roth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210542 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] AVX512: Add vmovntdqa

Along with the corresponding intrinsic and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210543 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Expand i1 SELECT_CC

il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210544 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Improved target combine rules for selecting horizontal add/sub.

This patch slightly changes the algorithm introduced at revision 210477
to fix a problem where the algorithm was producing incorrect code for 
the VEX.256 encoded versions of horizontal add/sub.

For these cases, we now try to split the two 256-bit vectors into
128-bit chunks before emitting horizontal add/sub dag nodes.

Added a new test case into haddsub-2.ll.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210545 91177308-0d34-0410-b5e6-96231b3b80d8
Do Materialize Floating Point in Mips Fast-Isel

Summary:
Implement materialize of floating point literals in Mips Fast-Isel

Reopened version of D3659

Test Plan: simplestorefp1.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4071

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210546 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the uses of AArch64TargetMachine and AArch64Subtarget from
AArch64FrameLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210548 91177308-0d34-0410-b5e6-96231b3b80d8
Move AArch64FrameLowering into the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210549 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit, wraps some lines to fit in 80 columns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210551 91177308-0d34-0410-b5e6-96231b3b80d8
Move DataLayout onto the AArch64 subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210552 91177308-0d34-0410-b5e6-96231b3b80d8
Remove caching of the subtarget for AArch64SelectionDAGInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210553 91177308-0d34-0410-b5e6-96231b3b80d8
Have AArch64SelectionDAGInfo take a DataLayout parameter rather
than a TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210554 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the cached little endian variable. We can get it easily off
of the DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210555 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel] Collect statistics about failing intrinsic calls.

Add more instruction-specific statistics about failing intrinsic calls during
FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210556 91177308-0d34-0410-b5e6-96231b3b80d8
Move AArch64SelectionDAGInfo down to the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210557 91177308-0d34-0410-b5e6-96231b3b80d8
Add a FIXME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210559 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Handle sign_extend and zero_extend to i64 with patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Handle fcopysign

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8