ARM: tegra: add SD wp-gpios to Dalmore DT

Dalmore can detect write-protect on the SD card. Add the required
DT entries to allow this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add SD wp-gpios to Venice2 DT

Venice2 can detect write-protect on the SD card. Add the required
DT entries to allow this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
Thierry, could you test this for me; my Venice2 has been sent away for
a few days for some rework. You should find that if you write-protect
your SD card, the kernel fails/panics trying to mount it as a r/w root
fs, whereas if the card is not write-protected, everything still works
fine. Thanks.
ARM: tegra: jetson-tk1: don't set mux func for GPIOs

When a Tegra pin is configured as a GPIO, the selected mux function is
irrelevant. Since we don't need to set the function for those pins,
don't do it!

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: update Venice2 pinmux

This re-imports the entire Venice2 pinmux data from the board's master
spreadsheet, thus tieing it to the primary definition of what is correct
for this board.

This also applies the same change as the previous patch does for Jetson
TK1: When a Tegra pin is configured as a GPIO, the selected mux function
is irrelevant. Since we don't need to set the function for those pins,
don't do it!

Signed-off-by: Stephen Warren <swarren@nvidia.com>
mmc: tegra: disable UHS modes

Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised
in SDHCI_CAPABILITIES_1.  While the Tegra SDHCI controller does support
these modes, they require Tegra-specific tuning and calibration routines
which the driver does not support yet.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
mmc: tegra: fix reporting of base clock frequency

Tegra SDHCI controllers, by default, report a base clock frequency
of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the
actual base clock frequency.  While this can be overridden by setting
BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just
set SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN and supply a get_max_clock()
callback to get the actual rate of the base clock.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: rebuild tegra_defconfig on next-20140424

This makes it easier to create isolated defconfig patches

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Rebuild multi_v7_defconfig on next-201404414

Signed-off-by: Stephen Warren <swarren@nvidia.com>
LOCAL HACK: tegra_defconfig changes

Signed-off-by: Stephen Warren <swarren@nvidia.com>
WIP: ARM: tegra: start work on Venice2 touchpad

Also added ISL light sensor to test I2C bus. Need to split this out
into a separate patch.

Import downstream driver from chromeos-3.10 so it initializes at all.

S-o-b: FIXME: a lot of downstream patches...
Signed-off-by: Stephen Warren <swarren@nvidia.com>
WIP: ARM: tegra: venice2 WiFi

Signed-off-by: Stephen Warren <swarren@nvidia.com>