i965: Don't store qpitch / 4 as mt->qpitch for compressed surfaces.

Broadwell requires software to specify QPitch in a bunch of packets,
so we decided to store it in the miptree.  However, when I did that
refactoring, I missed a subtlety: the hardware expects QPitch to be
"in units of rows in the uncompressed surface".

This is the value we originally compute.  However, for compressed
surfaces, we then divided it by 4 (the block height), to obtain the
physical layout.  This is no longer the QPitch Broadwell expects.

So, store the original undivided value in mt->qpitch, but continue to
use the divided value in brw_miptree_layout_texture_array().  For
non-Broadwell platforms, this should have no impact at all.

Helps fix Piglit's "getteximage-targets S3TC CUBE" test on Broadwell.

Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Duplicate gen7_atoms to gen8_atoms.

It's going to diverge significantly.  Starting out with a copy allows
future patches to change atoms one by one.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Bump generation assertions on workaround flushes.

These workaround flushes may not be necessary on Gen8.  Investigation is
needed.  Tentatively, let's do them out of caution.

v2: [chadv]
  - Comment that flush may not be needed.
  - Make assertion conditions symmetrical.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Update SF, SBE, and RASTER state for Broadwell.

The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.

v2: Set Force URB Read Offset bit.  Eventually the URB read offset
    should be set in 3DSTATE_VS, but that will require some refactoring.

v3: Rebase on viewport array changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.

v2: Use stencil->_WriteEnabled instead of setting
    GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE twice (suggested by Eric).

v3: Mask stencil->WriteMask and stencil->ValueMask with 0xff.  The field
    is only 8-bits, so we'd trip the new SET_FIELD assertion when core
    Mesa gave us a value like 0xFFFFFFFF.  The Gen7 code uses structure
    field widths to implicitly do this truncation.  Fixes Piglit tests.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v2]
i965: Add the new 3DSTATE_PS_BLEND state packet.

v2: Only set GEN8_PS_BLEND_HAS_WRITEABLE_RT if color buffer writes are
    enabled (caught by Eric Anholt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Rework 3DSTATE_VS for Broadwell.

v2: Remove incorrect MOCS shifts; rename urb_entry_write_offset to
    urb_entry_output_offset to closer match the documentation.

v3: Only emit a non-zero constant buffer read length when active.

v4: Add missing binding table counts (caught by Eric).

v5: Rebase on Paul Berry's changes to CurrentVertexProgram.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v4]
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.

v2: Fix setting of GEN8_PSX_ATTRIBUTE_ENABLE after rebases.

v3: Add missing binding table entry counts.  Don't worry about alpha
    testing or alpha to coverage when setting the "Kill Pixel" bit;
    those are specified in 3DSTATE_PS_BLEND (caught by Eric Anholt).
    Drop unused _NEW_BUFFERS.  Tidy comments.

v4: Rebase on Paul Berry's changes to CurrentFragmentProgram.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v3]
i965: Update STATE_BASE_ADDRESS for Broadwell.

v2: Fix missing "change" bit on instruction state base address
    (caught by Haihao Xiang).

v3: Add a perf_debug for missing MOCS setup, requested by Eric.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Rework vertex uploads for Broadwell.

v2: Emit a dummy 3DSTATE_VF_SGVS packet when not needed.

v3: Add WARN_ONCE and perf_debugs requested by Eric Anholt.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update 3DSTATE_CLIP for Broadwell.

Broadwell's winding order, polygon fill, and viewport Z test fields have
moved to DWord 1 of 3DSTATE_RASTER.

v2: Add a perf_debug for a future optimization and improve commit
    message (both suggested by Eric Anholt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update the code that disables unused shader stages for Broadwell.

v2: Also disable 3DSTATE_WM_CHROMAKEY for safety.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
i965: Update SOL state for Broadwell.

Unlike on Gen7, we can directly set the offset via the state packet.
We also -have- to: the kernel SOL reset code won't work anymore.

v2: Fix copy and paste mistake in buffer stride setup; drop stale
    comment (caught by Eric Anholt).  Add a perf_debug for missing
    MOCS setup.

v3: Rebase on Paul Berry's changes to CurrentVertexProgram.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v2]
i965: Rework SURFACE_STATE entries for Broadwell.

v2: Add missing SCS setting in gen8_emit_buffer_surface_state (caught by
    Eric Anholt).

v3: Use stored QPitch rather than recomputing it.

v4: Shift QPitch by 2 when setting it in the packet; bits 14:0 store
    bits 16:2 of the actual value (fixes myriads of cube and array
    texturing tests).  Also, only enable cube face bits for cubemaps
    (matches Chris Forbes' commit on master).  Port to use offset64.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update SF_CLIP_VIEWPORT for Broadwell.

It has additional fields to support clipping to the viewport even if
guardband clipping is enabled.

v2: Update for viewport array changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Update BLEND_STATE for Broadwell.

v2: Allow logic ops on all surface types.  The UNORM restriction was
    lifted with Haswell and I simply hadn't noticed.  Also, add missing
    BRW_NEW_STATE_BASE_ADDRESS dirty bit.  Both caught by Eric Anholt.

v3: Fix swapped per-RT DWord pairs.  Eliminates bizarre hacks.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.

XXX: Can probably just merge this in with the Gen7 code...
not really many changes.  OUT_RELOC64 and a few extra DWords (Qpitch)

XXX: lots of these parameters are garbage...

v2: Rebase on Paul's rename of NumLayers -> MaxNumLayers.

v3: Shift QPitch by 2 when storing it in the packet.  Bits 14:0 store
    bits 16:2 of the actual value.  Fixes tests.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update multisampling state for Broadwell.

On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
samples, pixel location, and the positions of each sample within a pixel
for each multisampling mode (4x and 8x).  It was also a non-pipelined
command, presumably since changing the sample positions is fairly
drastic.

Broadwell improves upon this by splitting the sample positions out into
a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN.  With
that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.

Broadwell also supports 2x and 16x multisampling, in addition to the 4x
and 8x supported by Gen7.  This patch, however, does not implement 2x
and 16x.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Update GS state for Broadwell.

This is quite similar to the Gen7 code.  The main changes:
 - 48-bit relocations
 - Thread count is specified as U/2-1 instead of U-1.
 - An extra DWord (DW9) with clip planes, URB entry output length/offsets
 - We need to program the "Expected Vertex Count" (VerticesIn)

v2: Set the number of binding table entries so they can be prefetched
    (requested by Eric Anholt).
v3: Add a WARN_ONCE for a missing workaround.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Disable 3DSTATE_WM_HZ_OP fields.

We'll need to do better than this when we implement multisampling, HiZ,
or fast clears...but for now, this will do.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>