arch/powerpc: Don't Try to Use NAND on Axxia 3500

Signed-off-by: John Jacques <john.jacques@lsi.com>
arch/powerpc: Corrected the Physical UART Address

Signed-off-by: John Jacques <john.jacques@lsi.com>
arch/powerpc: Removing Unnecessary Config File

Signed-off-by: John Jacques <john.jacques@lsi.com>
arch/powerpc: Corrected the Physical UART Address

Signed-off-by: John Jacques <john.jacques@lsi.com>
arch/powerpc: Removing Unnecessary Config File

Signed-off-by: John Jacques <john.jacques@lsi.com>
LSI AXM55xx: Fix PMU handler issue

The AXM55xx has the PMU IRQ lines from each core in a cluster OR'ed
together. As a workaround for this, a PMU handler extension was created
in the BSP to dynamically call irq_set_affinity() to rotate the PMU IRQ
assignment as needed, in order to maintain perf accuracy. However, with
the introduction of the Axxia GIC driver "slow" bus implementation,
irq_set_affinity() cannot be called directly from interrupt context.

Instead, the PMU IRQ handler extension is removed from the BSP and the
rotation of IRQ affinity is performed directly within the Axxia GIC
driver.

Signed-off-by: David Mercado <david.mercado@windriver.com>
Adding support for AXM3500 I2C driver

Signed-off-by: SangeethaRao <sangeetha.rao@lsi.com>
i2c: axxia: Add support for 10-bit addressing

Add support for I2c transfers using 10-bit address. The upper layer passes the
flag I2C_M_TEN to inform the driver that the msg->addr field is a 10-bit
address. The Axxia I2C controller will transmit a 10-bit address when the 5
most significant bits in address register 1 equals 5'b11110. The least
significant part of the address is then read from address register 2.

Signed-off-by: Anders Berg <anders.berg@lsi.com>
arch/arm: Add 8021Q Vlan Support to Axxia Preempt-RT

Signed-off-by: John Jacques <john.jacques@lsi.com>
arch/powerpc: Updated LSI Axxia Configs to Support 6 Cores

Signed-off-by: John Jacques <john.jacques@lsi.com>