ADC receiver logic inital version files added
ADC receiver logic first modified version
- Modules are prepared for PCL DAQ Card ADC
!Unit Interval must be set in BA_FSM_check_tr_FSM'!
Clock wizzard IP has been configured for the desired clocks
-ADC Frame clock pin,Bit clock pin,Data  lane  pis positions have been added

-Frame clock-System clock timing contraint has benn added
Data witdh correction
Deserializer bit inversion is now supported with inversion mask.
Inversion mask describes wich ISERDES output must be bit inverted because of the PCB routing. Bit inversion is performed with swapping output of the high-speed serial signal IBUFDS.
Data width correction
Power supply can not be controlled now. It has be changed because the AXI bus main clock signal is changed from PS_100MHz to ADC Frame clock.
ADC receiver modul instatiated