[mips][microMIPS] Implement microMIPS 16-bit instructions registers
Differential Revision: http://reviews.llvm.org/D5116


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220273 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructions
Differential Revision: http://reviews.llvm.org/D5117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220275 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement ADDU16 and SUBU16 instructions
Differential Revision: http://reviews.llvm.org/D5118


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220276 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the load analysis to allow finding available values which require
inttoptr or ptrtoint cast provided there is datalayout available.
Eventually, the datalayout can just be required but in practice it will
always be there today.

To go with the ability to expose available values requiring a ptrtoint
or inttoptr cast, helpers are added to perform one of these three casts.

These smarts are necessary to finish canonicalizing loads and stores to
the operational type requirements without regressing fundamental
combines.

I've added some test cases. These should actually improve as the load
combining and store combining improves, but they may fundamentally be
highlighting some missing combines for select in addition to exercising
the specific added logic to load analysis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220277 91177308-0d34-0410-b5e6-96231b3b80d8
[Thumb2] LDRS?[BH] cannot load to the PC

The Thumb2 LDRS?[BH] instructions are not valid when the destination
register is the PC (these encodings are used for preload hints).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220278 91177308-0d34-0410-b5e6-96231b3b80d8
[asan-asm-instrumentation] Fixed memory accesses with rbp as a base or an index register.

Summary: Fixed memory accesses with rbp as a base or an index register.

Reviewers: eugenis

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5819

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220283 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] NEON 32-bit scalar moves are also available in VFPv2

The 32-bit variants of the NEON scalar<->GPR move instructions are
also available in VFPv2. The 8- and 16-bit variants do require NEON.

Note that the checks in the test file are all -DAG because they are
checking a mixture of stdout and stderr, and the ordering is not
guaranteed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220288 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Avoid VSX FMA mutate when killed product reg = addend reg

With VSX enabled, test/CodeGen/PowerPC/recipest.ll exposes a bug in
the FMA mutation pass.  If we have a situation where a killed product
register is the same register as the FMA target, such as:

   %vreg5<def,tied1> = XSNMSUBADP %vreg5<tied0>, %vreg11, %vreg5,
                       %RM<imp-use>; VSFRC:%vreg5 F8RC:%vreg11 

then the substitution makes no sense.  We end up getting a crash when
we try to extend the interval associated with the killed product
register, as there is already a live range for %vreg5 there.  This
patch just disables the mutation under those circumstances.

Since recipest.ll generates different code with VMX enabled, I've
modified that test to use -mattr=-vsx.  I've borrowed the code from
that test that exposed the bug and placed it in fma-mutate.ll, where
it tests several mutation opportunities including the "bad" one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220290 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for addmod to mri scripts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220294 91177308-0d34-0410-b5e6-96231b3b80d8
Comment cleanup. NFC.

Don't duplicate names in comments and remove useless ones. Hopefully anyone
reading this knows what main is.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220298 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit
Fixing brief comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220299 91177308-0d34-0410-b5e6-96231b3b80d8
Silence a -Wcast-qual warning; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220300 91177308-0d34-0410-b5e6-96231b3b80d8
X86AsmInstrumentation.cpp: Dissolve initializer-ranged-for. MSC17 disliked it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220301 91177308-0d34-0410-b5e6-96231b3b80d8
[PBQP] Fix coalescing benefits

As coalescing registers is a benefit, the cost should be improved (i.e. made smaller) when coalescing is possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220302 91177308-0d34-0410-b5e6-96231b3b80d8
[PBQP] Check for out of bound access in DEBUG builds

It is just too easy to use a virtual register intead of a NodeId without a
compiler warning. This does not fix the fundamental problem, i.e. both
have the same underlying types, but increases the likelyhood to detect it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220303 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add pattern for bswap

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220304 91177308-0d34-0410-b5e6-96231b3b80d8
Convert two tests to use llvm-readobj.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220308 91177308-0d34-0410-b5e6-96231b3b80d8
remove function names from comments; NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220309 91177308-0d34-0410-b5e6-96231b3b80d8
Drop support for an old version of ld64 (from darwin 9).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220310 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Simplify FoldICmpCstShrCst

This function was complicated by the fact that it tried to perform
canonicalizations that were already preformed by InstSimplify.  Remove
this extra code and move the tests over to InstSimplify.  Add asserts to
make sure our preconditions hold before we make any assumptions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220314 91177308-0d34-0410-b5e6-96231b3b80d8