arch/powerpc: Updated Device Trees for Axxia Targets

Updated compatibility strings to work with the latest boot
loader.

Signed-off-by: John Jacques <john.jacques@lsi.com>
arch/powerpc: Use the right Machine Types in the Axxia NAND Driver

Signed-off-by: John Jacques <john.jacques@lsi.com>
arch/powerpc/boot/dts:
Checking in latest DTS files for ACP34xx/AXM35xx

Signed-off-by: SangeethaRao <sangeetha.rao@lsi.com>
arch/arm/mach-axxia:

Added calibrate_delay_is_known() such that only the first core
calculates delay calibration and rest of the cores use
the calculated value

Signed-off-by: SangeethaRao <sangeetha.rao@lsi.com>
arch/powerpc: Fix Up the MDIO Offset and Period on Axxia

If the MDIO offset and period are defined in the device tree,
use them.  Otherwise, don't change anything.

Signed-off-by: John Jacques <john.jacques@lsi.com>
arch/powerpc: Add a Work Around for Axxia 3500 Resets

The work around is to switch the PPCs back to the reference
clock before issuing a reset.  As described in the defect:

The reset_system issue is caused since the 6
counters are **NOT** reset by reset_system, but the
PLL and clock switch that controls the counters
**IS**.  Workaround for this: switch clk_ppc to
clk_ref before a reset_system or reset_chip. This
logically should work, BUT no STA work has been done
to validate this. Empirically, this seems to work.

Signed-off-by: John Jacques <john.jacques@lsi.com>