some fast math flags
mmc: decrease wakelock timeout
ARM: OMAP4: EMIF: implementation of errata i735 for PM timer

EMIF Power Management timer for Self Refresh will put the external SDRAM
in Self Refresh mode after the EMIF is idle for number of DDR clock cycles
that is set with REG_SR_TIM. The minimal value starts at 16 cycles.
However due to Errata i735, the minimal value is 512 DDR cycles as it is
required at OPP100 frequency.

Change-Id: If0748903580877aa4c1803f47e9134ee60c1dd75
Signed-off-by: Konstantyn Shlyakhovoy <x0155534@ti.com>
modified for tuna by faux123
ARM: 7632/1: spinlock: avoid exclusive accesses on unlock() path

When unlocking a spinlock, all we need to do is increment the owner
field of the lock. Since only one CPU can be performing an unlock()
operation for a given lock, this doesn't need to be exclusive.

This patch simplifies arch_spin_unlock to use non-exclusive accesses
when updating the owner field of the lock.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
HSMMC:Set disable timeout to 1ms

The disable timeout is reduced from 100ms to 1ms in order
to obtain aggressive power saving.

Cherry picked from p-android-omap-2.6.35 commit ID:
50df9d10a9b33c82ad02003686050b12b03d4dfe

Change-Id: Ieaa47d51396e7b92f6c1ba71e62900c58a05a26c
Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
MMC: OMAP HSMMC: Enable Auto CMD12

Configure OMAP HSMMC module to support Auto CMD12.
This will increase throughput during multi-block
command operations as CMD12 does not have to be
explicitly sent each time by software intervention.
Instead, hardware will send CMD12 after desired
number of blocks are transferred.

Change-Id: I37bf31399c80531d9fd76baa736a59a118c769b0
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
mmc: OMAP HSMMC: Add cmd23 support

Add support for set block count, close ended transfer

Change-Id: Iab7386e1171a42ebdf55306fbf291a3e6dd85b40
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
omap4-hsmmc : Adding ADMA support

Adds ADMA support for HSMMC controllers 1 & 2 on OMAP4
Ensure dma-sg list coming from block layer is unmapped after
every transfer completion.

Change-Id: I1b898f771a3119804920c5cd17ec9c4456c60916
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Signed-off-by: David Taylor <x0158378@ti.com>
mmc: omap: align adma and dma table entries

mmc->max_segs to core layer was set to 1024, but
adma table entry could only hold 512 entries. Increase
adma table entry size to 1024 from 512 to avoid mismatch.

Also set max_blk_count, max_req_size to what adma can
handle.

Change-Id: I8e08ee39bfa966bdf8a6c4374aea82b34fedcc62
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
mmc: omap: Increase number of blks we can handle

The above block layer is doing a "min" of max_req_size
and max_blk_count*512 before submitting each request.

As a result, the maximum size of request we are getting
is only 120*512 = 60KB even though each line in the
ADMA table can handle can handle that data alone.

So, we increase the max_blk_count we can handle. Also,
note that worst case is when above block layer gives
us 512 segments, in which there are 511 single block
entries, but one large block that is of size
mmc->max_req_size - (511*512) bytes.

In this case, we use the reserved 512 table entries
to break up the large request. Also adjust the
max_segs accordingly.

Change-Id: I733effdebea94f51a49bbf323950529afbb00dc4
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
omap-hsmmc: Implementation of i761 errata

Errata description:
Due to a bad behavior of an internal signal, the Card Error interrupt bit
MMCHS_STAT[28] CERR may not be set sometimes when an error occurred in the
card response.

Workaround:
After responses of type R1/R1b for all cards and responses of type R5/R5b/R6
for SD and SDIO cards, software must read two registers: MMCHS_RSP10 and
MMCHS_CSRE. When a MMCHS_CSRE[i] bit is set to 1, if the corresponding bit at
the same position in the response MMCHS_RSP10[i] is set to 1, the host
controller indicates a card error and software should proceed in the same way
as if a CERR interrupt would have been detected in the MMCHS_STAT register.

Note:
This errata is applicable for omap44xx.

Change-Id: Ib024bfb0624df04b7d6c61c129cbd9a34f919814
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
mmc: OMAP HSMMC: DDR support added.

OMAP HSMMC updated to support DDR mode

Change-Id: Ifb8643e264216edf514a7e31ec989316700ee322
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
mmc: Fix bug to enable DDR on MMC

MMC_CAP_UHS_DDR50 is an SD card feature and not
MMC feature. We don't have to check for this flag
to enable DDR on MMC. Checking for MMC_CAP_1.8V_DDR
is sufficient.

Change-Id: I6f44cb1f4dde6fe70cc816a2119c7b2b90944500
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
SMC: Update to AG01.06 production release

Last SMC update was to AG01.06 engineering release (see s_version.h)
this is the official patch to production AG01.06.

This update notably brings support for:
  * OMAP4 HW RNG - see new menuconfig option
  * GP devices are okay to be built with this SMC based on testing
      (even though it is not functional for GP devices, the SMC driver
      will no longer keep the device from entering suspend)

Change-Id: I974693ca73a038e2b547917e1a9556299a9bab11
Signed-off-by: Trusted Logic <smc_support@trusted-logic.com>
Signed-off-by: Jeremie Corbier <jeremie.corbier@trusted-logic.com>
Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>

Conflicts:
	security/smc/Makefile
SMC: Fix PA load error 0xffff3020

Fix "Error while loading the PA [0xffff3020]"

Improve synchronous public crypto.

WARNING: using this patch with an older PA binary (before MSHIELD
v1.7.5) will result in a PA load error. This patch is coupled with
changes in the secure PA (cache flush/invalidiation)

Change-Id: I3c3b7c41917b1146d6cb6f29ee33848eb9c3c0dc
Signed-off-by: Trusted Logic <smc_support@trusted-logic.com>
Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
SMC: Fix regression where AES1 clock would never be disabled

Change-Id: I3b620a573b2eee85c76036bcdab9f851ce9c7513
Signed-off-by: Trusted Logic <smc_support@trusted-logic.com>
Signed-off-by: Jeremie Corbier <jeremie.corbier@trusted-logic.com>
OMAP: SMC: Fix compile error if CONFIG_ION is not enabled

Change-Id: I541f0281916c008e0bf7dfe0069eaf700de37d42
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
SMC: Update to AG01.06p4 release

With this SMC driver version present in MSHIELD-DK 1.7.10 and using
corresponding PPA/PA, the crypto driver now uses DMA beyond a certain
data size threshold.

It fixes some statbility issues observed since introduction of DMA
in MSHIELD-DK release 1.7.2

        * start using GFP_ATOMIC instead of GFP_KERNEL in
                aes_sync_operate() and tf_digest_hw_perform_dma()
        * tf_clock_timer_start() now called in tf_clock_timer_cbis()
        * fixed potential memory leak in aes_sync_operate

Change-Id: Ifcb4653b0cad7dc2e5cf61bd58631c56d7738dd7
Signed-off-by: Trusted Logic <smc_support@trusted-logic.com>
Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
Signed-off-by: Srinivas Pulukuru <srinivas.pulukuru@ti.com>
SMC: Unlock aes_hwa_ctx lock in case of bad dma_map_sg

This release of the SMC package fixes PL310 accesses (See MSDK273
from MSHIELD)

In case of bad dma_map_sg, we silently fail. Be sure to call
spin_unlock_irqrestore before silently failing.

Change-Id: Ib6015c0710e56eae2bce341f263d62142f12ba3e
Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
SMC: Update UUID to match generic, common secure playback driver

Remove WVDRM prepends as this UUID is now generic.

Change-Id: I8b890d3f8227523635a394c9b02d409d597def8c
Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>