memory: emif: Move EMIF register defines to include/linux/

OMAP4 and AM33XX share the same EMIF controller IP. Although there
are significant differences in the IP integration due to which
AM33XX can't reuse the EMIF driver DVFS similar to OMAP4,
it can definitely benefit by reusing the EMIF related macros
defined in drivers/memory/emif.h.

In the current OMAP PM framework the PM code resides under
arch/arm/mach-omap2/. To enable reuse of the register defines move
the register defines in the emif header file to include/linux so that
both the EMIF driver and the AM33XX PM code can benefit.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP: DTB: Update IRQ data and add IPC regs for WKUP_M3

Allow interrupt for wkup_m3 to be set from DT. Also add regs for
IPC regs to allow pm code to communicate with wkup_m3.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: AM33XX: Reserve memory to comply with EMIF spec

SDRAM controller on AM33XX requires that a modification of certain
bit-fields in PWR_MGMT_CTRL register (ref. section 7.3.5.13 in
AM335x-Rev H) is followed by a dummy read access to SDRAM. This
scenario arises when entering a low power state like DeepSleep.
To ensure that the read is not from a cached region we reserve
some memory during bootup using the arm_memblock_steal() API while
maintaining the original call to omap_reserve.

A subsequent patch will pass along the location of the reserved
memory location to the AM335x suspend handler which modifies the
PWR_MGMT_CTRL register in the EMIF.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: AM33XX: Add assembly code for PM operations

In preparation for suspend-resume support for AM33XX, add
the assembly file with the code which is copied to internal
memory (OCMC RAM) during bootup and runs from there.

As part of the low power entry (DeepSleep0 mode in AM33XX TRM),
the code running from OCMC RAM does the following
1. Stores the EMIF configuration
2. Puts external memory in self-refresh
3. Disables EMIF clock
4. Executes WFI after writing to MPU_CLKCTRL register.

If no interrupts have come, WFI execution on MPU gets registered
as an interrupt with the WKUP-M3. WKUP-M3 takes care of disabling
some clocks which MPU should not (L3, L4, OCMC RAM etc) and takes
care of clockdomain and powerdomain transitions as part of the
DeepSleep0 mode entry.

In case a late interrupt comes in, WFI ends up as a NOP and MPU
continues execution from internal memory. The 'abort path' code
undoes whatever was done as part of the low power entry and indicates
a suspend failure by passing a non-zero value to the cpu_resume routine.

The 'resume path' code is similar to the 'abort path' with the key
difference of MMU being enabled in the 'abort path' but being
disabled in the 'resume path' due to MPU getting powered off.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: timer: Add suspend-resume callbacks for clkevent device

OMAP timer code registers two timers - one as clocksource
and one as clockevent. Since AM33XX has only one usable timer
in the WKUP domain one of the timers needs suspend-resume
support to restore the configuration to pre-suspend state.

commit adc78e6 (timekeeping: Add suspend and resume
of clock event devices) introduced .suspend and .resume
callbacks for clock event devices. Leverages these
callbacks to have AM33XX clockevent timer which is
in not in WKUP domain to behave properly across system
suspend.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP: omap_hwmod: Add handling of per suspend cycle hwmod idling

Needed to let the AM335x PM handle the IPs which need forced
standby transition during every suspend-resume cycle when
the corresponding driver is not compiled into the kernel. These modules
do not have MSTANDBY asserted by default so although they are idled at
boot, they lose context during suspend cycle and must be idled again.
Flag added to omap_hwmod to track devices that require per suspend cycle
idling. All flagged hwmods are added to a list and then removed in
omap_device as drivers are bound in order to avoid masking bugs in driver
suspend code. A post PM notifier then idles unbound hwmods after every
suspend cycle.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: AM33XX: Basic suspend resume support

AM335x supports various low power modes as documented
in section 8.1.4.3 of the AM335x TRM which is available
@ http://www.ti.com/litv/pdf/spruh73i

DeepSleep0 mode offers the lowest power mode with limited
wakeup sources without a system reboot and is mapped as
the suspend state in the kernel. In this state, MPU and
PER domains are turned off with the internal RAM held in
retention to facilitate resume process. As part of
the boot process, the assembly code is copied over to OCMCRAM
using the OMAP SRAM code.

AM335x has a Cortex-M3 (WKUP_M3) which assists the MPU
in DeepSleep0 and Standby entry and exit. WKUP_M3 takes care
of the clockdomain and powerdomain transitions based on the
intended low power state. MPU needs to load the appropriate
WKUP_M3 binary onto the WKUP_M3 memory space before it can
leverage any of the PM features like DeepSleep.

The IPC mechanism between MPU and WKUP_M3 uses a mailbox
sub-module and 8 IPC registers in the Control module. MPU
uses the assigned Mailbox for issuing an interrupt to
WKUP_M3 which then goes and checks the IPC registers for
the payload. WKUP_M3 has the ability to trigger an interrupt
to MPU by executing the "sev" instruction.

In the current implementation when the suspend process
is initiated, MPU interrupts the WKUP_M3 to let it know about
the intent of entering DeepSleep0 and waits for an ACK. When
the ACK is received MPU continues with its suspend process
to suspend all the drivers and then jumps to assembly in
OCMC RAM. The assembly code  puts the external RAM in self-refresh
mode and then finally execute the WFI instruction. Execution of the
WFI instruction triggers another interrupt to the WKUP_M3 which then
continues with the power down sequence wherein the clockdomain and
powerdomain transition takes place. As part of the sleep sequence,
WKUP_M3 unmasks the interrupt lines for the wakeup sources. WFI
execution on WKUP_M3 causes the hardware to disable the main
oscillator of the SoC.

When a wakeup event occurs, WKUP_M3 starts the power-up
sequence by switching on the power domains and finally
enabling the clock to MPU. Since the MPU gets powered down
as part of the sleep sequence in the resume path ROM code
starts executing. The ROM code detects a wakeup from sleep
and then jumps to the resume location in OCMC which was
populated in one of the IPC registers as part of the suspend
sequence.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: AM33XX: Hookup AM33XX PM code into OMAP builds

With all the requisite changes in place we can now enable the basic
PM support for AM33xx. This patch updates the various OMAP files
to enable suspend-resume on AM33xx.

Because the suspend resume functionality is different on AM33xx
than other OMAP platforms due to the need for M3 firmware and an
IPC channel to be in place, separate PM ops are used instead of
omap_pm_ops. These are now set using omap2_common_suspend_init
so the AM33xx can make a decision at runtime to enable suspend based
on the availabilty of aforementioned requirements.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: AM33XX: Improve wkup_m3 firmware handling

Create a wkup_m3_ops structure to handle both the pm wkup_m3 interrupt
callback and now a callback in the pm code for firmware loading. Now the
suspend ops are registered only after the wkup_m3 firmware has been
loaded and the version validated to avoid warnings during attempted
suspend if the M3 can not actually provide suspend support.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: AM33XX: Hard code virtual address for am33xx_dram_sync

Rev 1.5B of AM335x EVM has 1GB memory which prevents a 1:1 mapping from
physical to virtual memory. Hard code assignment of virtual address for
uncached memory page needed for emif power configuration (see commit
9461486d37643d0922f11fa3ef10006e99c25ad6 for further details).

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
arm: omap: wkup_m3: use FW_ACTION_HOTPLUG

with that, udev will load firmware for us.

Signed-off-by: Felipe Balbi <balbi@ti.com>
mailbox/omap: remove omap_mbox_type_t from mailbox ops

The type definition omap_mbox_type_t used for distinguishing
OMAP1 from OMAP2+ mailboxes does not really belong to the
ops, and has been cleaned up.

Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox/omap: add a parent structure common to all mboxes

A new structure, omap_mbox_device, is added to contain
the global variables pertinent to a mailbox h/w IP block.
This enables the support for having multiple instances of
the same h/w IP block in the SoC. The startup sequence for
each mailbox is also simplified along the way, removing the
usage of single global configuration variables for all h/w
instances.

Reviewed-by: Russ Dill <russ.dill@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox/omap: add support for parsing dt devices

Logic has been added to the OMAP2+ mailbox code to
parse the mailbox dt nodes and construct the different
mailboxes associated with the instance. The design is
based on gathering the same information that was being
passed previously through the platform data, except for
the interrupt type configuration information.

Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: dts: OMAP2+: Add mailbox nodes

The mailbox DT node data has been added for OMAP2420,
OMAP2430, OMAP3430/OMAP3630, OMAP44xx devices. Data
for OMAP5 and other SoCs will be added separately.

The mailbox static device initialization logic is also
adjusted for a DT boot.

Signed-off-by: Suman Anna <s-anna@ti.com>

Conflicts:
	arch/arm/boot/dts/omap2420.dtsi
	arch/arm/boot/dts/omap2430.dtsi
	arch/arm/boot/dts/omap3.dtsi
mailbox/omap: add code to support the wkupm3 operations

The WkupM3 mailbox used for triggering PM operations such as suspend
and resume on AM33x/AM43x is special in that the M3 processor cannot
access the mailbox registers. However, an interrupt is needed to be
sent to request the M3 to perform a desired PM operation. This patch
adds the support for this special mailbox through separate ops for
this mailbox. These ops are designed to have the WkupM3's Rx interrupt
programmed within the driver, during transmission of a message. The
message is immediately read back and the internal mailbox interrupt
acknowledged as well to avoid triggering any spurious interrupts to
the M3.

Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: dts: AM33xx: Add mailbox node

The mailbox DT node data has been added for AM33xx device, with
information added currently only for communicating with WkupM3
processor. The usr_id value in the DT node reflects the value
used for MPU like the rest of the SoCs. The driver logic will
be adjusted to account for the WkupM3 usr_id within the code.

Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox/omap: add registration support for multiple instances

The omap mailbox core currently keeps a global list of registered
mailboxes, and as such stores only the mailboxes from the last
registered mailbox IP instance. DRA7 is the first SoC where multiple
mailbox IP instances are present, and the mailbox clients are unable
to request mailbox devices present in any of earlier registered
IP instances.

The core registration logic is enhanced to support storing mailboxes
from multiple IP instances now. This is achieved by maintaining a list
of the mailbox IP instances, and storing the mailboxes per mailbox
instance. This allows the mailbox clients to successfully use a
mailbox from any IP instance.

Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: omap: edma: add suspend suspend/resume hooks

This patch makes the edma driver resume correctly after suspend. Tested
on an AM33xx platform with cyclic audio streams and omap_hsmmc.

All information can be reconstructed by already known runtime
information.

As we now use some functions that were previously only used from __init
context, annotations had to be dropped.

[nm@ti.com: added error handling for runtime + suspend_late/early_resume]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Daniel Mack <zonque@gmail.com>
Tested-by: Joel Fernandes <joelf@ti.com>
Acked-by: Joel Fernandes <joelf@ti.com>
ARM: OMAP2+: AM43XX: Add reserve function for AM43XX

AM33XX and AM43XX both share the same map_io function in
board_generic.c, but this function calls am33xx_dram_sync_init
which depends on a call to am33xx_reserve which is not set for
AM43XX. Add this to DT_MACHINE_INIT for AM43XX as it will
be needed later for suspend/resume but is needed now for boot.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>