i965/vec4: Switch to MOV, not OR, for GS_OPCODE_THREAD_END on Gen8.

Either should work.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/vec4: Port Gen8 SET_VERTEX_COUNT handling to vec4_generator.

Broadwell requires the number of vertices written by the geometry shader
to be specified in a separate register, as part of the terminating
message's payload.

This also means GS_OPCODE_THREAD_END needs to increment mlen.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/eu: Emulate F32TO16 and F16TO32 on Broadwell.

When we combine the Gen4-7 and Gen8+ generators, we'll need to handle
half float packing/unpacking functions somehow.  The Gen8+ generator
code today just emulates the behavior of the Gen7 F32TO16/F16TO32
instructions, including the align16 mode bugs.

Rather than messing with fs_generator/vec4_generator, I decided to just
emulate the instructions at the brw_eu_emit.c layer.

v2: Change gen >= 7 asserts to gen == 7 (suggested by Chris Forbes).
    Fix regressions on Haswell in VS tests due to type assertions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/eu: Refactor brw_WHILE to share a bit more code on Gen6+.

We're going to add a Gen8+ case shortly, which would need to duplicate
this code again.  Instead, share it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions.

According to the documentation, we need to set the source 0 register
type to IMM for flow control instructinos that have both JIP and UIP.
Out of paranoia, just make all flow control instructions use IMM;
there's no benefit to using ARF anyway, and it could trouble that's
difficult to diagnose.

See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the
analogous change in the gen8_generator code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/vec4: Drop gen <= 7 assertion in pull constant load handling.

I don't see any reason for this to exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/vp: Use the sampler for pull constant loads on Gen7/7.5.

This improves performance in Trine 2 at 1280x720 (windowed) on "Very
High" settings by 30% (in the interactive menu) to 45% (in the forest
by the giant frog) on Haswell GT3e.

It also now generates the same assembly on Gen7 as it does on Gen8,
which always used the sampler for both types.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Retype atomics to UD in Gen8 code generation.

Kind of a moot point since we're deleting Gen8 code generation, but
this at least helps make it match the Gen4-7 code.  It's probably more
reasonable than using float.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Switch to the EU emit layer for code generation on Broadwell.

Everything should be in place to unify code generation between Gen4-7
and Gen8+.  We should be able to drop the Gen8 generators at this point.

However, leave them hooked up for a brief moment, for testing and
comparison purposes.  Set GEN8=1 to use the old Gen8+ code generator
paths.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Never use the Gen8 code generators.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Delete the Gen8 code generators.

We now use the brw_eu_emit.c code instead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
vc4: Add support for the FLR opcode.
vc4: Fix off-by-one in texture maximum levels.

It's 2048x2048 that's the max, not 1024x1024.
vc4: Texture format support has nothing to do with VBO format support.

This was inherited from freedreno, but doesn't apply to us.
vc4: Stash some debug code for format support checks.

This can be useful for looking at context init setup and texture format
choices, and there's no reason for the silly retval computation we do if
you're not going to have this code (mostly from freedreno) around.
vc4: Declare what vertex formats we actually support.

We will support more than this eventually, but for now this makes u_vbuf
format-convert a few things (32-bit snorm and scaled, doubles) for us.
vc4: Claim the GL 2.1 minimum for 3D textures.

We don't actually do them (or even fake them) currently, but it does get
us a bunch of unrelated glean glsl1 tests passing, which previously would
error out due to glean assuming the minimums on a 3D texture that 2 of the
subtests use.
vc4: Drop the dump_fbo() routine.

Now that eglkms is working, and some tests are working under
PIGLIT_PLATFORM=gbm, I don't think I need this any more.
mesa: pull Khronos glcorearb.h header into include/GL/

Apps that only want to use core functionality should #include this
header.  This version covers everything up to OpenGL 4.5.

Reviewed-by: Matt Turner <mattst88@gmail.com>
docs: now distributing the GL/glcorearb.h header

Reviewed-by: Matt Turner <mattst88@gmail.com>