simple_dpram_sclk: change "TRUE"/"FALSE" parameter logic to 1/0
simple_dpram_sclk: add read enable logic

All users are also updated with a tied to 1'b1 signal
store_buffer: remove redundant fifo_raddr signal

This extra signal serves no purpose but to make the code harder
to read, connect read_pointer directly to raddr instead.
store_buffer: use re logic of ram instead of registering fifo_dout

Since the RAM already is keeping it's output data registered,
it's more area efficient to take advantage of this than
registering it in the store buffer.
Thanks to Florent Kermarrec for reminding me about this.
rf: use mor1kx_simple_dpram_sclk instead of rf_ram

With the addition of a read enable signal to
mor1kx_simple_dpram_sclk, it can act equivalent to rf_ram.
Swap all users of mor1kx_rf_ram and delete the module.
execute_alu: optimize barrel shifter

Instead of doing the actual shift operation seperately for each
shift/rotate operation, bit-reverse left shifts and only perform
a right shift.
The difference betweeen SRA, ROR and SRL is handled by
calculating a OPTION_OPERAND_WIDTH-bit word that is shifted
in from the most significant side of the result.
mor1kx_store_buffer: avoid unnecessary subtractor
change module definitions to verilog 2001 style
cappuccino/lsu: add option to disable store buffer

This adds a FEATURE_STORE_BUFFER parameter that let the user
make a speed (in terms of IPC) vs area choice.
top: change module definition to verilog 2001 style
add missing FEATURE_STORE_BUFFER to top module

This was missing in the previous commit that added this
feature parameter elsewhere.
cappuccino/wb_mux: remove unused lsu_valid_i input
execute_alu: remove & {OPTION_OPERAND_WIDTH{1'b1}} from mul

Several synthesis tools seems to be confused by the intention of this,
there have been reports about problems with Synplify and
ISE seem to add redundant logic.
execute_alu: Set result of disabled units to 0

Apart from being more sensible, it seems some tools can make
better optimization decisions from signals tied to 0.
dcache: minor whitespace fix
dcache: disable bypass for tag ram

There's always a one cycle 'reload' time accounted for in the
FSM, so using a write-on-read bypass is not necessary.
We still have to keep the bypass on the data ram,
since that is used when doing multiple byte-selected writes
to a single word in a row.
mor1kx_execute_alu: logic operation optimizations

Use a look-up-table instead of separately calculate and/or/xor.
execute_alu: tidy up logic optimization

The optimizations in bba8660
('mor1kx_execute_alu: logic operation optimizations'),
was provided as a proof-of-concept by Florent.
I however decided to pick that as is and do the tidy up in this
seperate commit.
This sprinkles some comments around, fixes a couple of coding
style issues and tries to make it a bit easier to read.
code clean up: remove trailing whitespaces
code clean up: remove empty lines at end of files