Updated clock divider to have a wider counter.
Added a reset to the counter
Initial commit of dual port RAM. This module will be mapped to Xilinx BRAM resources.
Initial commit of the draw lines module. This module can draw a single line between two input points. This module uses the bresenham module to calculate which pixels to illuminate. The illuminated pixels are represented by a value of 1 written to the RAM address corresponding to the x and y coordinates. This module has some signals for future implementation of the FIFO to handle drawing of multiple lines.
Modified the bresenham module for use with a display buffer. Updated the testbench to work with these changes.
Cleaned up draw_lines module and added comments
Cleaned up bresenham module and added comments.