Object/LLVMBuild.txt: Sort required_libraries by alphabetical order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212917 91177308-0d34-0410-b5e6-96231b3b80d8
NVPTX/LLVMBuild.txt: Add "Scalar" to required_libraries. It is really referenced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212918 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Update libdeps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212920 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] LINK_COMPONENTS: Add also corresponding MCTargetDesc and TargetInfo as well, when target names or "nativecodegen" are specified.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212921 91177308-0d34-0410-b5e6-96231b3b80d8
Support lowering of empty aggregates.

This crash was pretty common while compiling Rust for iOS (armv7). Reason -
SjLj preparation step was lowering aggregate arguments as ExtractValue +
InsertValue. ExtractValue has assertion which checks that there is some data in
value, which is not true in case of empty (no fields) structures. Rust uses
them quite extensively so this patch uses a 'select true, %val, undef'
instruction to lower the argument.

Patch by Valerii Hiora.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212922 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is
enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1)

This prevents the upper 32-bits of a double precision value from being moved to
the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure
that the code generated executes correctly regardless of the current FPU mode.

MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue
to use dmtc1.

Differential Revision: http://reviews.llvm.org/D4465


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212930 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no '.module oddspreg' is used

Differential Revision: http://reviews.llvm.org/D4486


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212932 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: remove unnecessary pseudo-instruction.

Sufficiently twisted use of TableGen lets us write patterns directly for f16
(as an i16 promoted to i32) -> f32 conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212933 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake][Win32.DLL] Let llvm_add_library(SHARED) link dependent libraries as PRIVATE.

For example, c-index-test.exe requires just libclang.dll (its import library).
When libraries in libclang were not PRIVATE but PUBLIC, c-index-test required libraries transitive by libclang.

Note, on mingw with BUILD_SHARED_LIBS, library dependencies would become more strict.
In principle, required libraries should be "required in its source file".

This will help to detect missing dependencies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212934 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves

Summary:
This is similar to r210771 which did the same thing for MTHC1.

Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the
wrong definitions.

Differential Revision: http://reviews.llvm.org/D4483


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212936 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1.

Summary:
This is because the FP64A the hardware will redirect 32-bit reads/writes
from/to odd-numbered registers to the upper 32-bits of the corresponding
even register. In effect, simulating FR=0 mode when FR=0 mode is not
available.

Unfortunately, we have to make the decision to avoid mfc1/mtc1 before
register allocation so we currently do this for even registers too.

FPXX has a similar requirement on 32-bit architectures that lack
mfhc1/mthc1 so this patch also handles the affected moves from the FPU for
FPXX too. Moves to the FPU were supported by an earlier commit.

Differential Revision: http://reviews.llvm.org/D4484


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212938 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags

Summary:
.bss, .text, and .data are at least 16-byte aligned.
.reginfo is 4-byte aligned and has a 24-byte EntrySize.
.MIPS.abiflags has an 24-byte EntrySize.
.MIPS.options is 8-byte aligned and has 1-byte EntrySize.

Using a 1-byte EntrySize for .MIPS.options seems strange because the
records are neither 1-byte long nor fixed-length but this matches the value
that GAS emits.

Differential Revision: http://reviews.llvm.org/D4487


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212939 91177308-0d34-0410-b5e6-96231b3b80d8
Revert: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags

This commit causes multiple lld tests to fail. Reverting while I investigate the issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212945 91177308-0d34-0410-b5e6-96231b3b80d8
Re-commit: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags

The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212946 91177308-0d34-0410-b5e6-96231b3b80d8
X86: remove temporary atomicrmw used during lowering.

We construct a temporary "atomicrmw xchg" instruction when lowering atomic
stores for widths that aren't supported natively. This isn't on the top-level
worklist though, so it won't be removed automatically and we have to do it
ourselves once that itself has been lowered.

Thanks Saleem for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212948 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-objdump: Handle BSS sections larger than the object file

The size of the uninitialized sections, like BSS, can exceed the size of
the object file.

Do not attempt to grab the contents of such sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212953 91177308-0d34-0410-b5e6-96231b3b80d8
CodeGen: add missing include

Found during windows unwinding work.  This header is indirectly included through
a chain leading through Support/Win64EH.h.  Explicitly include the header.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212955 91177308-0d34-0410-b5e6-96231b3b80d8
X86: correct 64-bit atomics on 32-bit

We would emit a libcall for a 64-bit atomic on x86 after SVN r212119.  This was
due to the misuse of hasCmpxchg16 to indicate if cmpxchg8b was supported on a
32-bit target.  They were added at different times and would result in the
border condition being mishandled.

This fixes the border case to emit the cmpxchg8b instruction for 64-bit atomic
operations on x86 at the cost of restoring a long-standing bug in the codegen.
We emit a cmpxchg8b on all x86 targets even where the CPU does not support this
instruction (pre-Pentium CPUs).  Although this bug should be fixed, this was
present prior to SVN r212119 and this change, so this is not really introducing
a regression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212956 91177308-0d34-0410-b5e6-96231b3b80d8
Remove GCC 3.3 workaround

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212960 91177308-0d34-0410-b5e6-96231b3b80d8
Update comments to include addrspacecast

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212961 91177308-0d34-0410-b5e6-96231b3b80d8