[FIX] Cut clock-xing path in Altera openMAC SDC

- Cut path from RMII to DMA clock domain
- Cut path from DMA to RMII clock domain

Change-Id: Ia75fd14368a3c7935afdf5c3dea8e52dcf8eb275
Reviewed-on: http://brateggevoat1/gerrit/2343
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix openMAC DMA address width

The openMAC DMA address width is now fixed to 32.

Change-Id: I7a9db7fab84c2535ebc8c82ee39ec1d4fc57c188
Reviewed-on: http://brateggevoat1/gerrit/2344
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix clock crossing component

This commit solves clock transfer issues with commands in tight
sequences. The fast and slow clock domain instances are redesigned using
a state machine. The fast clock domain instance uses a dedicated signal
for synchronizing the slow clock domain state machine.

Change-Id: Idc7a17423580b0eedcf2194f823136b95fb578a7