[X86] Improved target specific combine on VSELECT dag nodes.

This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to
convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1.
On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd.

Also, removed a target specific combine that performed a premature lowering of
VSELECT nodes to target specific MOVSS/MOVSD nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222647 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement disassembler support for 16-bit instructions

With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.

Differential Revision: http://reviews.llvm.org/D6149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222648 91177308-0d34-0410-b5e6-96231b3b80d8
Removing a variable that is initialized but never read. The original author has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222649 91177308-0d34-0410-b5e6-96231b3b80d8
Replace a comment that says 'unreachable' with llvm_unreachable in TableGen AsmWriter output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222650 91177308-0d34-0410-b5e6-96231b3b80d8
[Mips] Update MIPS relocations list

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222651 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0

Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.

Differential Revision: http://reviews.llvm.org/D5780


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222652 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions

Differential Revision: http://reviews.llvm.org/D5122


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653 91177308-0d34-0410-b5e6-96231b3b80d8
Added comment about llvm_execute_on_thread waiting for thread to complete.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222654 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Fix JRADDIUSP instruction

Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.

Differential Revision: http://reviews.llvm.org/D6365


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222658 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Don't create an unused instruction

We would create an instruction but not inserting it.
Not inserting the unused instruction would lead us to verification
failure.

This fixes PR21653.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222659 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding zxtb instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222660 91177308-0d34-0410-b5e6-96231b3b80d8
Adding const iterator to MCInst. http://reviews.llvm.org/D6359

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222661 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding zxth instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222662 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding aslh instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222668 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding asrh instruction, removing unused multiclasses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222670 91177308-0d34-0410-b5e6-96231b3b80d8
More long path name support on Windows, this time in program execution.
Allows long paths for the executable and redirected stdin/stdout/stderr.
Addresses PR21563.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222671 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Fix PR 21652 - copy st_other bits on symbol assignment

When processing an assignment in the integrated assembler that sets
a symbol to the value of another symbol, we need to copy the st_other
bits that encode the local entry point offset.

Modeled after MipsTargetELFStreamer::emitAssignment handling of the
ELF::STO_MIPS_MICROMIPS flag.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222672 91177308-0d34-0410-b5e6-96231b3b80d8
[asan/coverage] change the way asan coverage instrumentation is done: instead of setting the guard to 1 in the generated code, pass the pointer to guard to __sanitizer_cov and set it there. No user-visible functionality change expected

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222675 91177308-0d34-0410-b5e6-96231b3b80d8
Removing unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222676 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Fix clobber computation in A57LoadBalancing pass.

Extremely difficult to reproduce, so no test case included.
PR21637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222677 91177308-0d34-0410-b5e6-96231b3b80d8