misc: Add Fake RAM device

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
arm: xilinx_zynq: Add fake RAM device

In the PL region.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
HACK: xilinx_zynq: Change boot mode to SD

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
sd: sdhci: delete over-zealous check

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
sd: Delete over-zealous check

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
arm: Implement unassigned accesses as aborts.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
fake ram: Fix modulo bug

Squash me.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
tcg: Propagate Data vs Code information

All the way through to the memory API. This allows the memory API to
call cpu_unassigned_access with a correct exec argument. This in turn
allows for more correct error handling.

Just little endian, and only compile tested for ARM, which is the first
users of this. THe motiviation is for the CPU to be able to correctly
raise a data or prefetch abort on an unassigned access.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
HACK: zynq: chop OCM to only 64k and remove RAM

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
WIP

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Revert "tcg: Propagate Data vs Code information"

This reverts commit 66eee060243fbd268c5887eac692ca58bc9fbf1d.
HACK: Add global flag for whether TCG is live

And use it to switch between prefetch and data aborts for ARM.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>