ARM: zImage: ensure it is always a multiple of 64 bits in size

This is needed for proper alignment when the DTB appending feature
is used.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: I18dd4220a40984ab2551ca17a16db37193ffe80c
Original: 72bf0bce411d9df0935eb77256604212de8f89cc
Reviewed-on: http://git-master/r/108696
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: zImage: Allow the appending of a device tree binary

This patch provides the ability to boot using a device tree that is appended
to the raw binary zImage (e.g. cat zImage <filename>.dtb > zImage_w_dtb).

Signed-off-by: John Bonesio <bones@secretlab.ca>
[nico: ported to latest zImage changes plus additional cleanups/improvements]
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: I93c54694a59b357eb550587b94c986dcb19ab954
Original: e2a6a3aafa9862c4a4b59f2a59b8f923d64a680e
Reviewed-on: http://git-master/r/107422
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: zImage: make sure appended DTB doesn't get overwritten by kernel .bss

The appended DTB gets relocated with the decompressor code to get out
of the way of the decompressed kernel.  However the kernel's .bss section
may be larger than the relocated code and data, and then the DTB gets
overwritten.  Let's make sure the relocation takes care of moving zImage
far enough so no such conflict with .bss occurs.

Thanks to Tony Lindgren <tony@atomide.com> for figuring out this issue.

While at it, let's clean up the code a bit so that the wont_overwrite
symbol is used while determining if a conflict exists, making the above
change more precise as well as eliminating some ARM/THUMB alternates.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: I1590dcbb9789f20d4c56a1e1f7c40177acaa8a2d
Original: 5ffb04f6690d71fab241b3562ebf52b893ac4ff1
Reviewed-on: http://git-master/r/107767
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: zImage: allow supplementing appended DTB with traditional ATAG data

Some old bootloaders can't be updated to a device tree capable one,
yet they provide ATAGs with memory configuration, the ramdisk address,
the kernel cmdline string, etc.  To allow a device tree enabled
kernel to be used with such bootloaders, it is necessary to convert those
ATAGs into FDT properties and fold them into the DTB appended to zImage.

Currently the following ATAGs are converted:

	ATAG_CMDLINE
	ATAG_MEM
	ATAG_INITRD2

If the corresponding information already exists in the appended DTB, it
is replaced, otherwise the required node is created to hold it.

The code looks for ATAGs at the location pointed by the value of r2 upon
entry into the zImage code.  If no ATAGs are found there, an attempt at
finding ATAGs at the typical 0x100 offset from start of RAM is made.
Otherwise the DTB is left unchanged.

Thisstarted from an older patch from John Bonesio <bones@secretlab.ca>,
with contributions from David Brown <davidb@codeaurora.org>.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: Ifb96adf6976da0f518c9c2cdad6be85f94c8ad1c
Original: b90b9a38251e9c89c34179eccde57411ceb5f1aa
Reviewed-on: http://git-master/r/107423
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: zImage: gather some string functions into string.c

This is a small subset of string functions needed by commits to come.
Except for memcpy() which is unchanged from its original location, their
implementation is meant to be small, and -Os is enforced to prevent gcc
from doing pointless loop unrolling.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: Ib6fd21beb8ee8804e472fb4ff5eb1cbea2b8e877
Original: df4879fa2603fbf0804a80f9f146ef9023dd621f
Reviewed-on: http://git-master/r/107424
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: zImage: prevent constant copy+rebuild of lib1funcs.S

The rule to copy this file doesn't have to be forced.  However
lib1funcs.[So] have to be listed amongst the targets.

This prevents zImage from being recreated needlessly.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: I0ad0d4564835837abf15f0c590e8452bfef1c3a7
Original: 63d15148b6058ab0037343390e8918503ed81968
Reviewed-on: http://git-master/r/108698
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: 7017/1: Use generic BUG() handler

ARM uses its own BUG() handler which makes its output slightly different
from other archtectures.

One of the problems is that the ARM implementation doesn't report the
function
with the BUG() in it, but always reports the PC being in __bug(). The
generic
implementation doesn't have this problem.

Currently we get something like:

kernel BUG at fs/proc/breakme.c:35!
Unable to handle kernel NULL pointer dereference at virtual address
00000000
...
PC is at __bug+0x20/0x2c

With this patch it displays:

kernel BUG at fs/proc/breakme.c:35!
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP
...
PC is at write_breakme+0xd0/0x1b4

This implementation uses an undefined instruction to implement BUG, and
sets up
a bug table containing the relevant information. Many versions of gcc do
not
support %c properly for ARM (inserting a # when they shouldn't) so we
work
around this using distasteful macro magic.

v1: Initial version to replace existing ARM BUG() implementation with
something
more similar to other architectures.

v2: Add Thumb support, remove backtrace whitespace output changes.
Change to
use macros instead of requiring the asm %d flag to work (thanks to
Dave Martin <dave.martin@linaro.org>)

v3: Remove old BUG() implementation in favor of this one.
Remove the Backtrace: message (will submit this separately).
Rebase to linux-2.6.git master.

v4: Allow BUGS in modules (these were not reported correctly in v3)
(thanks to Stephen Boyd <sboyd@codeaurora.org> for suggesting that.)
Remove __bug() as this is no longer needed.

v5: Add %progbits as the section flags.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 87e040b6456fd3416a1f6831c1eedaef5c0a94ff)

Change-Id: Ic7692288dff6e4a15c732eb030295bd196a87fb4
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/117356
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
(cherry picked from commit 6708ffd0b44f4d09d8fe745471641545655091fb)
Reviewed-on: http://git-master/r/119328
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
arm: tegra: Add ATAG_SERIAL parsing

Bug 973078

Change-Id: I2860402c887db414717ce313101dc09e8b327f99
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>
Reviewed-on: http://git-master/r/108699
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: cache-l2x0: fix L2 maintenance for R3P1_50

Do flush and clear by set/way instead of by-way by enabling
errata 727915 for pl310 revision R3P1_50.
By-way maintenance doesn't work with enabled lp2_in_idle on
Tegra3 platform using R3P1_50 revision of pl310.

Debug register access causes hang when
CONFIG_TRUSTED_FOUNDATIONS is defined. Don't access those
regeisters if CONFIG_TRUSTED_FOUNDATIONS is defined.

bug 983964

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I76a3a9ef9dbcf86140ee26752202bf25542144e6
Reviewed-on: http://git-master/r/125153
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
tracing: Clock lock trace events

Add tracing for clock lock/unlock operations.

Bug 960307

Change-Id: Id5c2d8be25900bc701e5dcd73f87c068ab6e5894
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/122666
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
ARM: tegra: clocks: Frequency stats for SCLK/CBUS

This adds a frequency histogram of the frequencies that SCLK
and CBUS clocks go to over time. Stats are presented in the
debugfs at /d/clock_stats/cbus and /d/clock_stats/sclk only if
debugfs is enabled in config

Change-Id: Icae83329612958d8ed4318b2e10c487683d9d734
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/118380
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
arm: tegra: read board info from device tree

Read board_info data from device tree instead of ATAGs,
if we're booting with device tree.

Bug 1001225

Change-Id: I2d659252a6a91f723bf4bb6c74918774650b87e2
Original-Author: Dan Willemsen <dwillemsen@nvidia.com>
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/116604
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: Tegra: Omit L2 flush at disable

In Tegra kernel L2 is disabled only upon CPU cluster power down,
e.g. LP2 entry. Flushing L2 upon every LP2 entry is costly.
Since we are always in single core mode upon cluster power down
we can safely omit L2 flush upon L2 disable.

Change-Id: I27542b11e6133f3192a02440e5b14ea408b860fd
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/105625
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
arm: tegra: display: provide framebuffer clear function

Add tegra_clear_framebuffer function.

bug 1175957

Change-Id: I12c249e011ecd839bbe9c5371b8be6e8a4b27bba
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/170661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
arm: tegra: display: handle fbmem2 cmdline parameter

Parse and handle fbmem2 cmdline parameter.

bug 1175957

Change-Id: I0933825371bf13782e9f4364a4dba078929ae836
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/170662
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
arm: tegra: secureos: disable L2 as part of sleep CPU SMC

This is an alternate way to have the L2 disabled available with
later TL secureos versions.

In this version, the sleep CPU SMC which is the last one issued
before entering LP2 on CPU0, will also disable the L2 without a
flush of the secureos workspace.

Change-Id: I61c3caade6cb6f922b9d9f9ca0739bc6ae4e78cd
Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-on: http://git-master/r/128951
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: James Zhao <jamesz@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: tegra: power: Trace LP2 entry and exit

Add traces for measuring LP2 entry/exit times.

Bug 960304

Change-Id: I20bb0f8d55a7ed6f7e88e10d924871a3d09f2507
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/123313
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
ARM: tegra: Remove timer workaround

Reprogramming running timers may cause timer interrupt state
to get out of sync and result in lost timer interrupts.

Bug 950482

Change-Id: I83c9d735f9b041e8a57d73ba466f5f9c89ca1b89
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/111242
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: Ignore PmQos when disabled

The cpu hotplug drivers should only bother updating state or switching
to the G cluster if the driver is not disabled

Bug 1032096

Change-Id: Ice938b094bbf48fef47afa3915b1a48362fb256d
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/122859
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Revert "arm: tegra: scu: Enable IC and SCU standby"

This reverts commit b25193d5c3e2c59169c127d23b59123136cfefa7.
This CL is reverted as it causes write perf regression with lmbench(bw_mem)
benchmark.
Bug 1026077

Change-Id: I9858c88a6e846d2c3629f14c7cc62a7feb4f4528
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/125096
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>