try to separate some analysis from constructing the CFG. but it's proving difficult to identify which instructions are predecessors when simply given the list of pcf opcodes.
Merge branch 'release' of git+ssh://pequod.cs.virginia.edu/home/bt3ze/staging/lccyao2 into postprocessor
building up a cfg for pcf bytecode to do our exciting gate analysis.
branch instructions have two successors.
updating boundary case on last forward-flow input and remedying off-by-one error on branch's target successor. will need to address finding preds and succs for call,ret in order to construct full (forward-direction) cfg.
now including set of function names for building cfgs
preparing for gate analysis by directly looking at graph of gates (almost the circuit itself)
updates for completing the cfg with predecessors
updating flow graph to include predecessors. there's still a bug in the setmap implementation on insert (and maybe remove) but it appears remove is working much better.
cleanup, a few notes about gates and transitioning back to gate analysis
updates to setmap for getting set of key and set of values from a map
progress on building a proper cfg for pcf bytecodes with proper predecessors and successors. much of the forward cfg code rewritten.
would like to figure out why initbase isn't looking up main as it should be
initbase correctly finding main now. still need to handle other function calls, then cfg should be accurate (and capable of identifying some dead code)
update cfg for function calls. must figure out error preventing map-filter from indentifying function names.
builds CFG with preds and succs for function calls.
beginning cfg iteration for gate analysis. must build list of targets by dfs for proper analysis
fixes some bugs with sending functions to map-empty, and beginnings of dead gate analysis via whole program analysis for simple case of no functions
comments in gateanalysis and commenting out block
stable forward and backward cfg