msm: pm-8x60: Register sleep status driver before regulator

During hotplug, drivers wait for core to be power collapsed to turn off
the resources used by a core in CPU_DEAD notification. The kernel
thermal module which hotplugs the core in certain conditions is
registered in the arch_initcall(). To ensure that the CPU_DEAD waits for
sleep status to be set during hotplug, register the cpu sleep status
driver before the regulator driver.

To this effect, the sleep status driver is no longer made a child device
for pm-8x60 device.

Change-Id: I772521f4b3cd18e367aa44a41d60ef9735c99ef9
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: lpm: Alter the voting mechanism for lpm drivers

Currently the power management drivers monitor the sleep votes received
for certain system wide resources such as system clock and digital voltage
rail. By knowing the sleep vote and the available sleep time , latency
requests the low power management drivers (lpm_resources module) can alter
the sleep votes for those resources during RPM notified sleep modes.

Changing this method because this method requires a new low power level be
added for each combination of the system wide resources being monitored
and that each level be characterized (latency, power etc), this method is
not very scalable as the number of system resources being monitored by the
low power management driver increases. But most of all the decisions on
whether there is enough sleep time to enter these system wide sleep modes
(residency decisions) need to be made at RPM.

This change will remove the lpm_resources module altogether and remove all
low power levels beyond those pertaining L2 cache at lpm_levels.

CRs-Fixed: 490824
Change-Id: I255b696851074dcf7bed40b648c0eb3c5c4d0d6d
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
msm: spm: add intermediate LPM mode for L2 PC

Currently when the core decide to enter into "PC + L2 PC"
LPM mode it informs to RPM and there is a chance of
system can enter into either XO or VDDmin. But this LPM
mode take longer time to enter and exit. Because of this
limitation some of the usecases where there is a less
latency APPS proc stays at lower LPM level (i.e GDFS) and
causing more power consumption. To address this issue adding
an intermediate LPM mode where L2 goes to PC but not inform
to RPM.

CRs-fixed: 552743
Change-Id: I321ff260d5baf8ac44917d67e9c9dfd260c8d5ca
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: pm: cleanup spm code related to SAW2_V1

Code related to SAW2_V1 is removed. The relevant targets
are no more built on mainline.

Change-Id: Ie3f5a9f1dab0026b02e55384b6c620db774982b1
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: idle-v7: flush non secure L1 cache lines for l2 GDHS LPM mode

It is LPM driver(HLOS) responsiblity to flush non secure lines of
L1 cache when the core decide to enter a LPM mode where core get
powered off. But current code is not flushing the non secure lines
of L1 cache when the core decide to enter into L2 GDHS LPM mode.
This change addresses the flushing of non secure lines of L1 cache.

CRs-fixed: 555905
Change-Id: I721947386091875994bcb71bd8b9b9b793a72349
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: pm-8x60: Update the identity mapping for LPAE

The pm code uses a known stable page table with an identity mapping
for coming in and out of power collapse. This table currently assumes
a standard two level page table. This is incompatible with the new
format for LPAE. Update the code to handle both the LPAE and non-LPAE
page tables for power collapse.

Change-Id: I58097744134207fac49d7ab2147ba34f2f244a94
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
msm: mpm: Use clock API to prevent XO shutdown

When the active interrupts cannot be monitored by MPM during system
sleep modes, use linux clock APIs to vote against XO shutdown. Earlier
mpm driver relies on lpm resoures to overwrite the clock votes based on
enabled interrupts. This change decouples the MPM driver from the
lpm resources and thereby removing the dependency on RPM driver.

Change-Id: Ica5409ebb6744998303d84867f9b6d0243664b7e
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm:pm-8x60: Do not generate access flag faults for the kernel mappings

The pgd mapping (msm_pm_pc_pgd) generates Access flag fault whenever
this entry is read into the TLB for the first time. Add this flag to
the pgd mapping such that when the fault occurs, software resets the
Access flag to 1 in the translation table entry that caused the fault.
This prevents the fault from occurring the next time that memory
location is accessed.

Change-Id: I8d2ecc4d4005955ddeeaf3953ca1c445163b694c
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
msm: idle-v7: Add support to pass tz flag when core is hotplugged

When a core is hotplugged, trustzone migrates secure SPI to
the core that is online. Pass a flag to TZ indicating if it is
hotplugged or not.

Change-Id: I38d5a1987cdde9c6f3a456b7bb7726289ab0ad81
Signed-off-by: Priyanka Mathur <pmathur@codeaurora.org>
msm: pm: idle-v7 clean up

Legacy platforms are not expected to use the mainline
anymore. Unsupported targets are MSM7X01A, MSM7X25,
MSM7X27, MSM7X30, QSD8X50, MSM8X60, MSM8960,MSM8930,
APQ8064, FSM9XXX, MSM9615, MSM8625, MSM9625, MSM7X27A.

Remove unused code in idle-v7 and its related files.

Change-Id: If1fbf9eead91d3410c5c5e75cb92824b110b1138
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: idle: Use ARM suspend/resume APIs to restore during warmboot

ARM generic cpu_suspend/resume APIs restore the necessary CP15 registers
to a known state when resuming from a reset state. Use of generic
suspend/resume APIs allows the msm warmboot code to not care about
restoring core registers used by ARM kernel. Also, the PM subsystem no
longer needs to allocate page table or uncached memory to save CPU
registers.

While at it convert most of the assembler code into respective C
function except for warmboot code that executes with MMU turned off.
Also, the idle subsystem no longer needs to manage a  page table or
uncached memory to save CPU registers.

Change-Id: I78a75d0a3c703390eec476199c7ca2786360e12a
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
msm: pm: Rename pm-8x60.c to msm-pm.c

pm-8x60.c doesn't accurately reflect the current list of targets that
are supported. So renaming them to msm-pm.c to be more inline with the
msm chipsets.

Change-Id: Iefa8150885f8da136de7cba4a122ec901a171a02
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: clock: Add a CXO voter for the LPM driver

The Low Power Mode resources driver needs to vote for
CXO in certain conditions. Add a voter clock for that
driver to the 9625/8226/8610 clock drivers.

Also, while we're here, create voter clocks for CXO
wherever necessary.

Change-Id: I07c9aed2ab67a58d296041a62049de63277995cd
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
ARM: dts: msm8974: Update MPM mapping for GIC interrupts

Some interrupts can be bypassed during xo shutdown
as they are not responsible for wakeup. Update MPM
mappings with such a list.

CRs-fixed: 553244
Change-Id: Ic88cac341b5dcf4f710f34893bb38d746c457757

Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
ARM: dts: msm: Add CX regulator Phandle to MDP node

The Phandle might change for different
versions of the msm8974 chip. Add the Phandle
of CX regulator to only v2 version.

Change-Id: Ifce120fcb349360e36c4ea74bcaf5ea14e1dece5
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
ARM: dts: msm: Add MSM8974v2 DT support for RPM master stats driver

Add support for rpm master stats driver for MSM8974v2.
RPM master stats driver is used to read the individual
master stats from the RPM MESSAGE RAM.

CRs-Fixed: 517589
Change-Id: Ida8ab41857d144207336d1c844dced8e365003f2
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: spm: Replace msm_spm_apcs_set_vdd with msm_spm_set_vdd

msm_spm_apcs_set_vdd() is used to set the vdd of a gang rail through the
L2 SAW2. Remove this api and overload the msm_spm_set_vdd() call with a
dont-care 'cpu' argument instead.

Detect if the target is configured to use L2 SAW as APCS master using a
boolean property in the device tree.

Change-Id: Ib8d9605474fa44d5223985ec8cb1040cde230592
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
msm: clock: Add a new API to print registers for debugging

clk_debug_print_hw() will format a list of register names and values, and
output the result to either the kernel log or a seq_file.

Change-Id: Ic225eb0261818faaee91b42955f2a517e927a30b
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: clock-debug: Add support to show all the enabled clocks

Add a new debugfs file <debugfs>/clk/enabled_clocks to show all the
currently enabled clock, their rate and their dependency chain.

Example output:
cat /sys/kernel/debug/clk/enabled_clocks
Enabled clocks:
        gcc_lpass_q6_axi_clk:1:1 [0]
        gcc_mss_q6_bimc_axi_clk:1:1 [0]
        gcc_mss_cfg_ahb_clk:1:1 [0]
        gcc_boot_rom_ahb_clk:1:1 [0]
        xo_a_clk:2:2 [19200000]
        gpll0_ao:2:2 [600000000]
        kpss_ahb_clk_src:1:1 [19200000] ->
xo_a_clk:2:2 [19200000]
        bimc_msmbus_a_clk:1:1 [400000000] ->
bimc_a_clk:1:1 [400000000]
        qdss_clk:4:4 [1]
        qdss_clk:4:4 [1]
        qdss_clk:4:4 [1]
        qdss_clk:4:4 [1]
        qdss_clk:4:4 [1]
           ....
Enabled clock count: 42

Change-Id: I6eda59c7e61b77518676e3aa93895ccb792176ac
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
msm: clock-8226: Fix compile errors when CONFIG_DEBUG_FS is removed

Declare variables used only if CONFIG_DEBUG_FS is defined within ifdef
statements.

CRs-fixed: 554999
Change-Id: I28d2104ebd7baba8a151fc34946463f2429709b1
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>