WIP: Analog Buffers, Analog Converters and Linker Enhancement

### Analog Libraries.
#### Todo

- [x] Linker Enhancement using callback to bind function with connection.
- [ ] Linker Modification to link at Bus level itself ( Better efficiency )
- [x] Analog to Digital Converter [ SAR - Based  ADC / IEEE 754 Converters]
- [x] Digital to Analog Converter
- [x] Attenuable Analog Buffer Block
- [ ] Signal Generator - Sin, 
- [x] Tests

#### Summary of Changes

Most of the blocks implemented in this PR reflects the functionality and usability of the linker module.

##### 1. Analog to Digital Converter

IEEE64 IEEE32 Generic Signed / Unsigned 16, 8 , 4 bit outputs
'Links' the passed input with analog connector.
Uses AnalogBuffer modules in input and output.

##### 2. Digital to Analog Converter
    Links passed Bus to IEEE64 IEEE32 Generic Signed / Unsigned 16, 8 , 4 bit inputs
    Links an analog Bus to output.
    Uses AnalogBuffer modules in input and output.

##### 3. Linker Enhancement
The following  enhancements are made to linker module:
* The linker will now bind DiGraph edges ( connection links ) with a method that will be invoked before updation of  the link.
* AutoUpdater is separated from the `connections_updater` which runs as thread. AutoUpdater is a container for the Connections DiGraph and static methods to update the same.

###### SAMPLE  CODE:
```
.
.
def trigger(self):
    augmented_inputs = [ i*0.2 for i in self.inputs ]
    outputs.set_logic_all(augmented_inputs)
.
.
.
def set_inputs(self, inputs):
    AutoUpdater.remove_link(self.inputs)     # Removes all links to / from self.inputs
    AutoUpdater.add_link(inputs, self.inputs, bind_to = ModuleName.trigger, params = [ self ] )
    # This essentially makes the connection_updater_thread call the self.trigger() before updation.
```


##### 4. Analog Buffer Bank Module [ `buffers.py` ]
    A multi-input externally enabled attenuation ( in voltage db ) capable Buffer is implemented.
    This module Helps to link external inputs with input logic.
    Overall this is how Modules are implemented using the Busses, Buffer, Linker and trigger.
```
                                                       MODULE
                           __________________________________________________________________
ExternalInputs-----------> |--- [ Buffer ] --->[ Inner Transfer Function ]--->[Buffer ] --- |------------>ExternalOutputs
         |          |      |_______|_______________________|_____________________|__________|       |         |
         |          |              |                       |                     |                  |         |
         V          V              V                       V                     V                  V         V
        Bus ------[AU]------------BM----------------trigger block----------------BM---------------[AU]-------Bus
                    |                                   *                                           |
                    |________________callback___________|__________callback_________________________|



*AU - AutoUpdater - linker.py
*BM - AnalogBuffer - buffers.py
```

Sample Code for A2D and D2A Converters [ From `__doc__` string ]

For IEEE 754 Conversions Refer - [Wikipedia](http://en.wikipedia.org/wiki/IEEE_floating_point) and [this](http://babbage.cs.qc.cuny.edu/IEEE-754.old/Decimal.html)
A2D

```
    >>> input_analog   = Bus(Connector(voltage = 6.4))
    >>> input_analog.set_type(analog = True)
    >>> output_digital = Bus(16)
    >>> VREF           = Connector(voltage = 5.0)
    >>> GND            = Connector(voltage = 0)
    >>> a2d_16bit = A2D(input_analog, output_digital, 3, VREF, GND, scale = 0.5)
    >>> time.sleep(0.5) # To allow conversion to take place.
    >>> print output_digital.get_logic_all(as_list = False)

    0b1010001111010111

    >>> input_analog[0].set_voltage(4.2)
    >>> time.sleep(0.5) # To allow conversion to take place.
    >>> print output_digital.get_logic_all(as_list = False)

    0b0110101110000101

    >>> ieee_64bit = Bus(64)
    >>> a2d_IEEE64 = A2D(input_analog, ieee_64bit, 5)
    >>> time.sleep(0.5) # To allow conversion to take place.
    >>> print ieee_64bit.get_logic_all(as_list = False)

    0b0100000000010000110011001100110011001100110011001100110011001101

```

D2A

```
    
    >>> output_analog   = Bus(Connector(voltage = 6.4))
    >>> output_analog.set_type(analog = True)
    >>> input_digital = Bus(16)
    >>> input_digital.set_logic_all('0110101110000101')
    >>> VREF           = Connector(voltage = 5.0)
    >>> GND            = Connector(voltage = 0)
    >>> d2a_16bit = D2A(input_digital, output_analog, 3, VREF, GND, scale = 2)
    >>> time.sleep(0.1) # To allow conversion to take place.
    >>> print output_analog[0].get_voltage()

    4.19998168945

    >>> ieee_64bit = Bus(64)
    >>> ieee_64bit.set_logic_all('0b0100000000011001100110011001100110011001100110011001100110011010')
    >>> ieee_packed = Bus(1)
    >>> ieee_packed.set_type(analog = True)
    >>> d2a_ieee64 = D2A(ieee_64bit, ieee_packed, 5)
    >>> time.sleep(0.1)
    >>> print  ieee_packed[0].get_voltage()

```

##### 5. Signal Generator

The source.py module is re written to give inputs / outputs via the Analog Busses and Connectors.

The Signal generator can generate - Sin, ( and Cos), Square, Ramp, TTL and Triangular.

###### Example : 
```
```

@debugger22 Will this cause all the clock instances to share  a common lock ?