RFC: SystemVerilog extension in the verilog parser

This request serves only as a platform for discussing the SystemVerilog extension in the verilog parser.
At the moment I'd like to open the following two discussion points:

1. http://sourceforge.net/p/ctags/support-requests/17/ - The person who opened this request did a fine job in the creation of a SystemVerilog parser. It would be nice if he could be invited to participate in this discussion to see if we could work together to merge our efforts.
2. Class objects - I'd like to know if you have any suggestions on how the parser could be aware of class declarations and dynamically identifying of which class an object instance is.

Thanks,
Vitor