amd/agesa/f10: Invalid inline asm in gcc-intrin.h

Forward port commit:
db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm

Change-Id: Ic1bd19087a4500ba0ca9e312ea351e301ab42518
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7301
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
amd/agesa/f12: Invalid inline asm in gcc-intrin.h

Forward port commit:
db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm

Change-Id: Ife26fb5eca5164e72b5e55eba90757253765b633
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7300
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
amd/agesa/f15: Invalid inline asm in gcc-intrin.h

Forward port commit:
db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm

Change-Id: I52da16b39293c8aeff150db83b8b1aeaa232c205
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7299
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
intel/bd82x6x: Add new current for native USB ports

Change-Id: I88ef36b94b961a318d280d8de1b8721fcbeb93b0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7237
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
gigabyte/ga-b75m-d3h: Add new Intel mainboard

This is based on LENOVO X230 port. Board boots to linux via SATA.

Remaining Issues:

1. Native raminit sometimes fails with "timC write discovery failed"
   even without changing the ram configuration.
   I suggest altering the native raminit code so that it reboots
   if that message appears to give a chance for the boot process to recover.

2. VGA does not work.
   Native graphics initialization only supports LVDS and the
   VGA Option ROM still hangs when run in SeaBIOS

3. USB does not work.
   SeaBIOS/GRUB2 do not detect devices connected to USB ports

4. Sound needs corrected codec verb settings

Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7020
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
SeaBIOS Makefile.inc: Remove build dir for uppermem option

The build directory got removed while my patch was in flight and I
didn't notice when I submitted it.

The uppermemory change was added in
commit 4d7d25f38a - http://review.coreboot.org/#/c/6364

The output directory was changed for everything else in
commit ab11a6a94c - http://review.coreboot.org/#/c/6460

Change-Id: Ib8311f694280d305e826adbb76e3e7b722b30e0f
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7298
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
inteltool: refine GPIO and PMBASE/TCO printing on Ibex Peak/5 Series

Nicolas Reinecke was noticing that in my Lenovo T410s logs the GPIO*3
settings were missing. This led to some investigation and this patch, thanks!

Change-Id: I7ba28aa00d10f988a7fe81e61d2e216b54a11006
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/7239
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
intel_wifi: Export the SMBIOS structure required by intel driver.

Change-Id: I22984a1bc7ca3be6593143af4fce8d5bfe469837
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7295
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Revert "gigabyte/ga-b75m-d3h: Add new Intel mainboard"

Breaks abuild and is dependent on WIP, is WIP itself.

This reverts commit d7d0c8134854cba72f0c3fe25946b27ce0364b43.

Change-Id: I8b589b41632696aa4570abcceab5f3a3b0784649
Signed-off-by: Vladimir Serbinenko  <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7319
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
AGESA f12: Add "const" modifiers

Apply commit 283ba78415 to f12 (literally, plus one adaptation).

Change-Id: Ied7891806e269320caf968cae3de3dc792c5f8fd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7312
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
AMD boards: constify romstage variables

That takes them out of .data

Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7313
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
cbfstool: Convert cbfs-mkstage.c into pelf

Change cbfs-mkstage to use parsed elf instead of calling elf_headers. That
allows us to have access to the complete elf including the string table.

Change-Id: Ie767d28bdf41af38d1df0bce54bc0ada45123136
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7303
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
cbfstool: Add option to ignore section in add-stage

Allow add-stage to have an optional parameter for ignoring any section. This is
required to ensure proper operation of elf_to_stage in case of loadable segments
with zero filesize.

Change-Id: I49ad62c2a4260ab9cec173c80c0f16923fc66c79
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7304
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
romstage: Pass .car.data as ignored section while adding romstage

We don't want segment for .car.data section to be considered while elf_to_stage
transformation is being done. Thus, use -S option for add-stage.

Change-Id: I04868c892e3aa94113189b012d284d52bacea5f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7305
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
build: fetch submodules as required

Also document the unusual git feature we employ for 3rdparty

Change-Id: I1d1c986f9d1c4dd8db687d746dbdeb510679141a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7243
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
superio/ite: Use common dispatch for pnp entry/exit functions

We already have these implemented under superio/common, use
those instead of this copy-paste syndrom.

Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7310
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
mainboard/dmp/vortex86ec: Unused variable in romstage.c

Change-Id: I9cc549b7862ee535928bd06b5fb4bd38bb67a992
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7279
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Redundant addr '&' operator on func ptr's in struct initiator

Bring code inline to be consistent with the rest of coreboot.

See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase,
'expressions that refer to functions get converted to pointers to
those functions'

Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7290
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
amd/agesa/f16kb: Invalid inline asm in gcc-intrin.h

Forward port commit:
db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm

Change-Id: Ia857f76d3782aea07e09df1352eeb286e40b2689
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7302
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
inteltool: Add support for Haswell ULT and Lynx Point LP

Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5
Reviewed-on: http://review.coreboot.org/7275
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>