target-ppc: Add Store Quadword Conditional

This patch adds the Store Quadword Conditionl (stqcx.) instruction
which is introduced in Power ISA 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
[agraf: fix compile error when !TARGET_PPC64]
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Add Instruction Flag

This patch adds a flag that will be used to tag the Altivec instructions
introduced in Power ISA Version 2.07.

The flag is added to Power8 model since P8 supports these instructions.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Update AVR Structure

This patch updates the ppc_avr_t data structure to include elements for
signed 64-bit integers and (conditionally) unsigned 128 bit integers.
These elements will be in instructions models later on in this patch series.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Add GEN_VXFORM3

This patch adds generator macro for Altivec instructions that have 3
source AVR operands.  The macro is similar to the 2 operand form.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions

Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode bit.  However, QEMU for PowerPC uses
bits 0-5 and 21-30 for opcodes and not bit 31.

This patch introduces macros that will handle this situation by injecting
an auxiliary handler which decodes bit 31 in invokes one of two standard
handlers.  Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions

This patch adds a macro to insert an entry into the opcode table for Altivec
Power ISA Version 2.07 instructions.  The macro is similar to the GEN_VXFORM macro
except that it tags the entry with the PPC2_ALTIVEC_207 flag rather than
PPC_ALTIVEC.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions

Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode but also use bit 21 as an actual Rc
bit.  QEMU for PowerPC typically uses bits 0-5 and 21-30 for opcodes.

This patch introduces a generator macro that injects an auxiliary handler
which decodes both bits 21 and 31 and invokes one of four standard
handlers.  Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* flags are supported.

This patch also introduces a macro to insert two entries into the opcode
table -- one for bit 21 equal to 0 and one for bit 21 equal to 1.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Logical Instructions

This patch adds the Vector Logical Instructions that are introduced
in Power ISA Version 2.07: veqv, vnand and vorc.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo

This patch adds two Altivec unsigned doublword modulo instructions that
are introduced in Power ISA Version V2.07:

  - vaddudm : Vector Add Unsigned Doubleword Modulo
  - vsubudm : Vector Subtrace Unsigned Doubleword Modulo

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers

This VMUL_DO macro provides support for the various vmule* and vmulo*
instructions.  These instructions multiply vector elements, producing
products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit
elements and produces a 16 bit unsigned element.

The existing macro works correctly for the existing instructions (8-bit,
and 16-bit source elements) but does not work correctly for 32-bit
source elements.

This patch adds an explicit cast to the multiplicands, forcing them to be
of the target element type.  This is required for the forthcoming patches
that add the vmul[eo][us]w instructions.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions

This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:

  - Vector Multiply Even Unsigned Word (vmuleuw)
  - Vector Multiply Even Signed Word (vmulesw)
  - Vector Multiply Odd Unsigned Word (vmulouw)
  - Vector Multiply Odd Signed Word (vmulosw)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: vmuluw Instruction

This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm)
instruction.

The existing VARITH_DO macro is re-used to (trivially) instantiate
the helper code.

Since bits 21-31 of any vmuluwm instruction is 137, the instruction
is coded as a dual to vmulouw (bits 21-31 = 136).

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes

This patch adds the Vector Count Leading Zeroes instructions introduced
in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Population Count Instructions

This patch adds the Vector Population Count instructions introduced in Power
ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions

This patch adds the Vector Minimum and Maximum Doubleword instructions
that are introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Pack Doubleword Instructions

This patch adds the Vector Pack Doubleword instructions introduced in
Power ISA Version 2.07:

 - Vector Pack Signed Doubleword Signed Saturate (vpksdss)
 - Vector Pack Signed Doubleword Unsigned Saturate (vpksdus)
 - Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum)
 - Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Unpack Signed Word Instructions

This patch adds the Unpack Signed Word instructions introduced in
Power ISA Version 2.07:

  - Vector Unpack High Signed Word (vupkusw)
  - Vector Unpack Low Signed Word (vupklsw)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Merge Instructions

This patch adds the Vector Merge Even Word (vmrgew) and Vector
Merge Odd Word (vmrgow) instructions introduced in Power ISA
Version 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts

Existing code in the VROTATE, VSL and VSR macros for the Altivec rotate and shift
helpers uses a formula to compute a bit mask used to extract the rotate/shift
amount from the VRB register.  What is desired is:

    mask = (1 << (3 + log2(sizeof(element)))) - 1

but what is implemented is:

    mask = (1 << (3 + (sizeof(element)/2))) - 1

This produces correct answers when "element" is uint8_t, uint16_t or uint_32t.  But
it breaks down when element is uint64_t.

This patch corrects the situation.  Since the mask is known at compile time, the
macros are changed to simply accept the mask as an argument.

Subsequent patches in this series will add double-word variants of rotates and
shifts and thus take advantage of this fix.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions

This patch adds the vector doublword rotate and shift instructions
introduced in Power ISA Version 2.07:

  - Vector Rotate Left Doubleword instruction (vrld)
  - Vector Shift Left Doubleword (vsld)
  - Vector Shift Right Doubleword (vsrd)
  - Vector Shift Right Algegbraic Doubleword (vsrad)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>