Add support for MIPS r3 and r5.

2014-06-03  Andrew Bennett  <andrew.bennett@imgtec.com> 

	* config/mips/mips-cpus.def: Add mips32r3, mips32r5, mips64r3 and
	mips64r5.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_compute_frame_info): Changed if statement
	to use mips_isa_rev rather than ISA_MIPS32R2.
	* config/mips/mips.h (ISA_MIPS32R3): New define.
	(ISA_MIPS32R5): New define.
	(ISA_MIPS64R3): New define.
	(ISA_MIPS64R5): New define.
	(TARGET_CPU_CPP_BUILTINS): Added support for ISA_MIPS32R3, ISA_MIPS32R5,
	ISA_MIPS64R3 and ISA_MIPS64R5.
	(MIPS_ISA_LEVEL_SPEC): Added support for mips32r3, mips32r5, mips64r3
	and mips64r5.
	(MIPS_ISA_SYNCI_SPEC): Likewise.
	(ISA_HAS_64BIT_REGS): Added ISA_MIPS64R3 and ISA_MIPS64R5.
	(LINK_SPEC): Added mips32r3 and mips32r5.
	* config/mips/t-isa3264 (MULTILIB_MATCHES): Map mips32r3 and mips32r5
	to mips32r2; and mips64r3 and mips64r5 to mips64r2.
	* config/mips/t-mti-elf (MULTILIB_MATCHES): Likewise.
	* config/mips/t-mti-linux (MULTILIB_MATCHES): Likewise.
	* config/mips/t-sde (MULTILIB_MATCHES): Likewise.
	* config/mips/t-sdemtk (MULTILIB_MATCHES): New define.
	* doc/invoke.texi: Document mips32r3, mips32r5, mips64r3 and mips64r5.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211173 138bc75d-0d04-0410-961f-82ee72b054a4
Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.

        * config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
        New pattern.
        * config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
        (aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
        * config/aarch64/iterators.md (REVERSE): New iterator.
        (UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
        (rev_op): New int_attribute.
        * config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
        vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
        vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
        vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
        vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
        vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
        vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
        Replace temporary __asm__ with __builtin_shuffle.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211174 138bc75d-0d04-0410-961f-82ee72b054a4
[Patch, microblaze]: Add optimized lshrsi3

When barrel shifter is not present, the immediate value
is greater than #5 and optimization is -OS, the
compiler will generate shift operation using loop.

Changelog

2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn

ChangeLog/testsuite

2014-02-12  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.

Signed-off-by:Nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add INIT_PRIORITY support

Added TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.

These macros allows users to control the order of initialization
of objects defined at namespace scope with the init_priority
attribute by specifying a relative priority, a constant integral
expression currently bounded between 101 and 65535 inclusive.

Lower numbers indicate a higher priority.

Changelog

2013-11-26  Nagaraju Mekala <nagaraju.mekala@xilinx.com>

 * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
   microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
   TARGET_ASM_DESTRUCTOR.

Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add supervisory call support

A function can be executed in supervisory mode when a function
is declared with svc_handler attribute.

If a function with svc_handler is called, the processor switches
to supervisory mode and executes. After executing the function
it returns to normal mode.

Same feature can also be invoked with svc_table_handler attribute
but this attribute will accept a service ID, to be used for
calling the function.

Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Increase max alignment to please the testsuite

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Disable fivopts by default

Turn off ivopts by default. Interferes with cse.

Changelog

2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>

 * gcc/common/config/microblaze/microblaze-common.c
   (microblaze_option_optimization_table): Disable fivopts by default.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Use bralid for profiler calls

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Enable DWARF exception handling support.

Changelog

2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
            David Holsgrove <david.holsgrove@xilinx.com>

 * common/config/microblaze/microblaze-common.c: Remove
   TARGET_EXCEPT_UNWIND_INFO definition.
 * config/microblaze/microblaze-protos.h: Add
   microblaze_eh_return prototype.
 * gcc/config/microblaze/microblaze.c: (microblaze_must_save_register,
   microblaze_expand_epilogue, microblaze_return_addr): Handle
   calls_eh_return
   (microblaze_eh_return): New function.
 * gcc/config/microblaze/microblaze.h: Define RETURN_ADDR_OFFSET,
   EH_RETURN_DATA_REGNO, MB_EH_STACKADJ_REGNUM, EH_RETURN_STACKADJ_RTX,
   ASM_PREFERRED_EH_DATA_FORMAT
 * gcc/config/microblaze/microblaze.md: Define eh_return pattern.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Fixed missing save of r18 in fast_interrupt.

Register 18 is used as a clobber register, and must be stored when
entering a fast_interrupt. Before this fix, register 18 was only
saved if it was used directly in the interrupt function.

However, if the fast_interrupt function called a function that used
r18, the register would not be saved, and thus be mangled
upon returning from the interrupt.

Changelog

2014-02-27  Klaus Petersen <klauspetersen@gmail.com>

 * gcc/config/microblaze/microblaze.c: Check for fast_interrupt in
   microblaze_must_save_register.

Signed-off-by: Klaus Petersen <klauspetersen@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Add MicroBlaze to check_profiling_available

Testsuite, add microblaze*-*-* target in check_profiling_available
inline with other archs setting profiling_available_saved to 0

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Add MicroBlaze pattern for dg-function-on-line

Add MicroBlaze specific pattern for checking line number and
generation of funtion in dg-function-on-line, in line with
mips method.

Changelog/testsuite

2014-02-13  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/lib/scanasm.exp (dg-function-on-line): Add
   MicroBlaze specific pattern.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Allow MicroBlaze .weakext pattern in regex match

Extend regex pattern to include optional ext at the end of
.weak to match the MicroBlaze weak label .weakext

ChangeLog/testsuite

2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
   pattern to take optional ext after .weak.
 * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Update MicroBlaze strings test

for new scan-assembly output resulting in use of $LC label

ChangeLog/testsuite

2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
   to include $LC label.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Add MicroBlaze to target-supports for atomic builtin tests

MicroBlaze added to supported targets for atomic builtin tests.

Changelog/testsuite

2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/lib/target-supports.exp: Add microblaze to
   check_effective_target_sync_int_long.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[LOCAL]: For dejagnu static testing on qemu, suppress warnings

about multiple definitions from the test function and libc in line
with method used by powerpc. Dynamic linking and using a qemu binary
which understands sysroot resolves all test failures with builtins

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[LOCAL]: Testsuite - explicitly add -fivopts for tests that depend on it

(test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt exist in 4.6 branch)

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[LOCAL]: Quick fail g++.dg/opt/memcpy1.C

This particular testcase fails with a timeout. Instead, fail it
at compile-time for microblaze. This speeds up the testsuite without
removing it from the FAIL reports.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[LOCAL]: Testsuite - builtins tests require fpic

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>