msm_fb: display: Make sysfs read request interruptible

Change blocking sysfs read request to be interruptible and protect
vsync timestamp value to prevent corruption.

Change-Id: I510d84134b0ab70d17729e8c53c91fa926035142
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
msm_fb: display: add dtv base layer swap

Add dtv base layer swap between border fill pipe
and rgb pipe to support hdmi as primary display.

Change-Id: I127a301385d5d83e5d06507869132c6e124cc94f
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm_fb: display: return fail if pipe still staged

Pipe is not un-staged from mixer when it is unset.
It expects a pan_display() to un-stage it out of mixer.
Return fail at overlay_set() if pipe was still stage
at mixer.

CRs-fixed: 399193, 393979
Change-Id: I562f6e133bb239b30f4f53669dbf1cc5ddf80d02
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm_fb: display: check pipes queued before enter wait_for_completion

Timing generator will not be turned on if there are no pipes queued.
Therefore wait_for_completion may never be completed if there have
no pipes queued.

Change-Id: Iafba086e4ba20b31470c9fd385c4f5c474ecadcf
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm_fb: display: Enable scaling bit while setting x-flip bit

To enable left-right flip x-scaling bit should be set for
MDP 4.2 and above versions. This fixes the issue when RGB layer
pipes are not properly rotated.

Change-Id: I0afae4aecde39ce3ac4dcbefc0bda93510e7d18a
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Revert "msm_fb: display: add fput_light to frame buffer"

This reverts commit a84a41a0d5f6b98b8dd53545b74541a76ca18d95.

Change-Id: I0b8ebc8ed122d99e8731ac79b046dae18edfb48b
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
msm_fb: display: add fput_light to frame buffer

Frame buffer's (fb0) ref_count need to be balanced. overlay_play()
increase fb0's ref_count (fget_light). This patch will decrease fb0's
ref_count by calling fput_light after commit

(cherry picked from commit 7d136bef71281855cd224ccc967e4e95286f5356)

Change-Id: I9ba6d5c73cdb29c32a665d2b7b90df996c5b39e6
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm_fb: dsiplay: fix frame buffer f_count leak

Frame buffer maintains a reference count (f_count) which increased
by fget() and decreased by fput(). overlay play will apply
fget() to frame buffer if it was the soruce buffer and fput()
will be applied to it after pipe commit done. However there has
extra fput() apply to frame buffer at the time pipe is freed.
This patch fix the problem by  clear MDP_MEMORY_ID_TYPE_FB from
pipe's flags to avoid extra fput() applying to frame buffer.

CRs-fixed: 411394
Change-Id: Ib2b72e6277480b5ace23cda554be485d9d477b3d
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
video: msm: Reset MDP clock/bw rates during panel on

 * These need to be reset so that the correct rate is calculated on
   wakeup. Without this, underrun will occur.
 * Via Samsung's JB code drop.

Change-Id: I02ab8a220db442c35eb5838ab6a986467d0f44ad
msm_fb: display: fix iommu leak during base layer swap

Retain RGB1 iommu information during  base layer swap
so that iommu used by RGB1 can be freed back to pool later.

Change-Id: Ibed85179284743dc8a9d1434f0c81626b0567e16
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm: kgsl: Add new sysfs node to list GPU clock frequencies

Add a new sysfs node to communicate available GPU clock frequencies
to userspace for the power daemons.

Signed-off-by: Anshuman Dani <adani@codeaurora.org>
(cherry picked from commit 0e80b365d2b6e15344a774667a1e273edb2d64ff)

Conflicts:

	drivers/gpu/msm/kgsl_pwrctrl.c

Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
(cherry picked from commit 9ca738c3c746017e5a4c8d5fe64e1ed3e6128cc1)

Change-Id: I623a36148ae86a9a527f28e7d768535f67ceaa01
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
msm: kgsl: Fix the address translation ranges for GPU IOMMU

Set the address translation to happen via ttbr0 for GPU IOMMU till
address 0x80000000 instead of 0x40000000. Also, adjust the size of
virtual pool so that it does not allocate an address greater
than 0x80000000.

CRs-fixed: 401364
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
(cherry picked from commit 54aa5c08ddbdb2255102758237f8717302558c63)

Change-Id: I051a2197fc6a56285d153f3200b4b4500035de7f
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
Merge "hayabusa: update defconfig" into jellybean
arm: gic: Configure the GIC to run in secure mode

Configure the GIC to run in secure mode and handle
secure as well as non-secure interrupts. This patch
adds an API to configure an IRQ as a secure IRQ so that
it can be treated as an FIQ in the secure mode.

Change-Id: Ic3321e76c95a4c10d6287ba418e84623e7004cb1
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
arm: fiq: Provide empty stubs for fiq functions

A driver using fiq functions should be usable on targets
with or without CONFIG_FIQ enabled. Instead of making code
dependent on #ifdef CONFIG_FIQ, add empty stubs for the fiq
functions.

Change-Id: Ie8b1905ba53664d99bd707be3c83291c97eb1066
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
ARM: gic: Add support to access GIC in secure mode

Currently gic secure mode is enabled for all the v7 cpus.
For 8x25 we do not want to access GIC in secure mode as
we are observe issues of not able to clear the pending clear
registers when we come out of power collapse.

The Kconfig should make it flexible for targets who want to
support GIC in secure/non-secure modes.

Change-Id: Id7c85f5b741346233993966752607e5c4fb23e74
Signed-off-by: Taniya Das <tdas@codeaurora.org>
arm: gic: Register irqdomain after adding it

Recently a change was added to break apart irq_domain_add() into
two functions. The first creates the domain, and the second
registers it.

This change abides to this new interface and registers the
GIC irq_domain after creating it.

Change-Id: I34c6a1f56dc27113a9b72f0fefa577276f91bbc8
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
arm: gic: Check for error code on irq_domain_add

This API now returns an error. Since gic_init_bases() is called
early on, there's probably not a whole lot we can do here except
send a warning.

Change-Id: I2835dacfa191db0ce70434de23e6ee540fe33b57
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
ARM: gic: Add spinlocks for SGIR/AIR/EOI for 8625

On 8625 due to bug in AHB MUX on hready, back to back write followed
by read (from any CPU) on QGIC2 registers (SGIR(WO) ,IAR(RO) and
write on EOI(WO)) cause the read data to get corrupted on AHB bus.

Due to this whenever a valid irq has occurs, and dispatched to the cpu
interface but still cpu reads the IAR as 0x0 and that particular IRQ
becomes active.
But due to incorrect irq id (read as 0x0), IRQ handler will not do
proper EOI for that particular interrupt and thus it gets trapped
in the active state.

Below is the qgic register dump from CPU-1, in this particular case
we see that SGI-3 is not getting clear as cpu reads this as 0x0.

AZSD:C0000200| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000280| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000300| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
AZSD:C0000380| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................

As the interrupt gets trapped, no other interrupt received on the core is
services any more causing the system hang.

CRs-Fixed: 349219
Change-Id: Icad2c65114377a08984b1032566cfba811bb4ca8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
ARM: gic: Move GIC based code out from mpm-8625

Moving code which modifies the GIC registers. As there is no global
lock in gic code, moving the code out.

Change-Id: I85a2bd580dbeefc942a3307f3c0cad8b1da509b7
Signed-off-by: Taniya Das <tdas@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/mpm-8625.c
	arch/arm/mach-msm/platsmp-8625.c