01/30/2014 set ALCTtx drive setting back to UCLA standard, also changes to DPS clocks (9 DPS -> 4 DPS w/BUFG feedbacks)
02/10/2014 use ODDR to bring out clock, alct_rxclock, alct_txclock on testled 1:3
02/12/2014 bring out alct_rx_posneg & alct_tx_posneg  on testled 5 & 7;  modify clk feedback circuit
           in clock_ctrl.v: exchange names CLOCK --> CLOCK_FB   and   CLOCK_DPS --> CLOCK
02/16/2014 tuned logic for clock_lac & changed inputs to ODDR's for ALCT Tx (now "Same Edge")
04/03/2014 merge Jason's changes from above with Yuriy's code for extended MPC results register in VME