DMAC driver changes for SDRDC application

- enable REGMAP_MMIO and REGMAP automatically
- add a buswidth parameter to set copy_align
- add a device-id parameter to differentiate channels
Enable generic scatterlist chaining for Zynq

SDRDC application uses scatterlist chaining for large one-shot DMA transfers
Improve handling of max-speed below minimum

When the client's requested speed was below the minimum speed based on the clock
configuration, the driver would select illegal values for the BAUD_RATE_DIV
field and set a reserved bit which the TRM says should stay 0.  The resulting
behavior was that received bytes would be shifted down one bit and have their
MSB set (so 0x0A would become 0x85).

This change stops at the lowest speed the controller can acheive, which may be
higher than the client's requested speed but is more likely to work.  The speed
calculation is also run if the BAUD_RATE_DIV field is 0, which is not supported
according to the TRM.
Fixes for Xilinx AXI-DMA driver

- Add support for the xlnx,device-id property and add it to the value used to
  select a DMA channel in systems with multiple AXM DMA controller instances
- Fix a bug where setting xlnx,sg-include-stscntrl-strm to 1 would remove the
  XILINX_DMA_IP_DMA bit from xdev->feature
AD9361 driver changes for SDRDC use

- Allow operation without oops if conv->indio_dev is unset, skips most of
  ad9361_dig_interface_timing_analysis() so manual tuning is required
- Amend global clock names with a per-instance suffix to allow for multiple
  AD9361 devices in a system
- Check for any clock init failure, and remove working clocks before abort
- Print reset GPIO pin and product ID/revision register on init, for debugging
  and bringup.