Make use of TimerA more robust on MSP430

Since on MSP430 architecture, TAIV interrupt has the least priority, we can have race conditions where hwtimers fail to fire just after an overflow, because ```timer_round``` variable hasn't been incremented in due time.

This basically forces us to use CCR0 (which has highest interrupt priority) as the overflow detector, sacrificing one hwtimer instance.

The occasion was seized to try to make the MSP430-dependent hwtimer implementation more flexible, to prepare for the use of TimerB (which offers more CCR registers).

We also try to increment ```timer_round``` every 32K timer cycles, making it basically a seconds counter.
Some decision in that PR would be necessary for that.