Merge branch 'sunxi-base' into sunxi-clk-base
clk: sunxi: factors: automatic reparenting support

This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
clk: sunxi: unify APB1 clock

This commit unifies the APB1 mux with the APB1 clock, using the new
factors infrastructure.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
ARM: sunxi: dt: unify APB1 clock

With the new factors infrastructure in place, we can unify apb1 and
apb1_mux as a single clock now.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
clk: sunxi: Implement muxable AHB clock

sun5i and sun7i have a mux to change the AHB clock parent, this commit
adds support for it on the driver.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
ARM: sunxi: dt: Update AHB clock to be muxable on sun[57]i

sun5i and sun7i have a mux to select the parent clock for AHB. This
commit implements the required changes on the device trees.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
ARM: sun7i: fix PLL4 clock and add PLL8

Allwinner reworked the PLL4 clock in sun7i; so we need to change the
compatible. Additionally, PLL8 is compatible with this new PLL4
implementation, so let's add a node for it as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
clk: sunxi: add support for DRAM gates

This implements support for the DRAM gates on sun4i, sun5i and sun7i
platforms. The gate information has been obtained from the A10, A13 and
A20 user manuals, while an Allwinner code release has been used for
A10S.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
ARM: sun4i: Add DRAM gates

This commit adds the required node for DRAM gate support on the sun4i
device tree.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
ARM: sun5i: Add DRAM gates

This commit adds the required node for DRAM gate support on the sun5i
device trees.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
ARM: sun7i: Add DRAM gates

This commit adds the required node for DRAM gate support on the sun7i
device tree. Not surprisingly, the A20 shares the same gates as it's
sun4i counterpart, the A10.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
clk: sunxi: Add some more bounds checking and warning messages

If something is requesting a rate we can simply not fulfill, let the
user/developer know via a warning, and do something sane meanwhile.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
clk: sunxi: Implement MMC phase control

Signed-off-by: Emilio López <emilio@elopez.com.ar>
ARM: sunxi: clk: export clk_sunxi_mmc_phase_control

Signed-off-by: Hans de Goede <hdegoede@redhat.com>